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Expediting processor verification through testbench infrastructure reuse

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Alan M. Feldstein
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re: Expediting processor verification through testbench infrastructure reuse
Alan M. Feldstein   3/13/2011 8:51:57 PM
Our approach with the commercial software we are developing is to deliver a reusable architectural verification environment just for SPARC-V9 designs. We don't concern ourselves with any implementation-specific features of the DUT, only the ISA. We treat the DUT as a black box that is simply required to obey the architectural manual. We stimulate it with SPARC instructions and observe architecturally visible state only. Of course, the processor project will require product-specific tools too for other areas of the verification space. But our software is intended to be used off-the-shelf to find architectural bugs in any DUT that aspires to be SPARC-V9 compliant. Alan M. Feldstein, Owner / Architectural Verification Engineer, Cosmic Horizon

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David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.