It took five years for the industry to migrate from PCI Express 1.0 (introduced in 2002) to PCI Express 2.0 (introduced in 2007). Now, the next wave is here - PCI Express 3.0.
Known commonly as PCIe Gen 1, Gen 2 or Gen 3, reflecting on successive generations, it’s the preferred interconnect for scalable systems, devices and applications such as high-end graphics, fault-tolerant clusters, and storage IO sharing networks. PCIe Gen 3 features 8Gb/s bandwidth, which is double that of Gen 2, while preserving compatibility with software and mechanical interfaces. It also has better provisions for reduced power, signal and data integrity, new transmit and receive equalization methods, and clock data recovery.
Anticipating this new wave of Gen 3 systems and devices, new test tools will be needed to ensure the hardware and software are functional and work together. This article will survey those hardware and software tools for validation, compliance and general testing.
Because PCIe Gen 3 requirements are more stringent than those for Gen 2, these new test tools must manage a new level of complexity and challenges. PCIe Gen 3’s dominant feature is to ensure reliable transmission at 8Gb/s in spite of signal distortion, closed eyes and inter-symbol interference. New test tools must account for encoding similar to 128b/130b, effects of receiver and transmitter equalization, and dynamic negotiation of transmitter equalization at boot-up time. At the same time, PCIe Gen 3 is backward compatible with both Gen 2 and Gen 1.
PCIe Gen 3 test tools can span across five parts of the interconnect technology’s specification: electrical, configuration, link, transactions and platform BIOS. Because PCIe Gen 3 supports backward compatibility with Gen 2 and Gen 1, not all existing PCIe test tools have become obsolete; most tools still can be reused.
In general, the types of test tool used will depend on the applications and which tools are available at the time of the product is being qualified. The PCI-SIG is a good source for designers to discover and evaluate compliance tests tools. Its compliance test equipment library shows equipment that it has approved and recommended to others for use. Using equipment from the list reduces risks, saves evaluation time, and ensures common industry-standard test platforms.
Because PCIe Gen 3 tools employ cutting-edge technologies and require substantial investments, careful selection of the test tools used is critical. Eight suggested evaluation criteria are:
Industry leadership: Selecting from the top two or three vendors is not only feasible but also recommended. Industry leaders usually have advantages of track records, name brands and market acceptance.
Interoperability: Tools must be backward-compatible with PCIe Gen 2 and Gen 1. As new PCIe Gen 3 systems and devices are available, the tools must interoperate with them as well.
Usability: The tools must feature user-friendly interfaces and be easy to deploy.
Portability: Tools need to be flexible, modular, allow expansion and can interoperate across different multiple operating systems, BIOS, CPUs, and chipsets.
Robustness: Test tools must have a high degree of reliability.
Compliant specs and clear upgrade path – Winning tools incorporate new spec changes quickly, without negatively impacting customer designs.
Feature-richness:Test tools not only must run faster and better, they should be flexible to support multiple applications and allow designers to go deep when monitoring the internals of their designs. Additionally, low-power support, low CPU utilization and large memory buffers are desirable. Other compelling features include light in weight, small dimensions, and industry compliance and certification.
Warranty, technical support and training: Insurance protection and ancillary support services are critical.
I know this article is mostly about protocol analyzers, but Table 1 really should include a LeCroy scope model, perhaps a WM816Zi or WM820Zi. An option for these scopes actually lets them do PCIe decode for Gen1, Gen2 and Gen3 - on the scope.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.