It is not uncommon to see an article or read a paper that says something like “In 2010 there were 2,500 ASIC design starts versus 90,000 FPGA design starts.” And we say to ourselves: “Well, that’s jolly interesting.” And then we quote these values to each other in conversations at the water cooler and use them in our own papers and articles, but where do these numbers actually come from and how accurate are they?
Note: As an aside, you may also be interested in my column FPGAs: System gates or logic cells/elements? (Click Here to see that column).
Of course we all know that there are fewer ASIC design starts today as compared to say five or ten years ago. This is primarily because designing ASICs at the latest and greatest technology nodes is an increasingly complex, resource-intensive, time-consuming, and expensive hobby.
It’s also common knowledge that there are more FPGA design starts today than there were five and ten years ago. In addition to the fact that the use of electronics is increasing dramatically in almost all walks of life, this is primarily due to the fact that today’s FPGAs have higher capacity and higher performance coupled with lower power consumption (relatively speaking), all of which means that FPGAs can now play in applications and markets that were previously “owned” by ASICs and other devices.
I don’t know about you, but what I would really like to see would be a graph showing these trends over the last few years. Perhaps something like the one shown below (NOTE that this is a totally fictitious graphic created using no data from no source whatsoever – it’s just something that I threw together, so please don’t use these numbers for anything meaningful).
But where can we find accurate data for this sort of thing? The problem is that we’re comparing “apples with oranges,”
and the more you delve into this topic the more your brains start to leak out of your ears. Just wait; you’ll see what I mean. But “nothing ventured, nothing gained,” as the old saying goes, so let’s start by defining a few terms, setting a few boundaries, and seeing where we end up…
What does the term FPGA encompass?
On the Field-Programmable Gate Array (FPGA)
side of the fence, there are a variety of underlying configuration technologies we need to consider – in particular SRAM-based, Flash-based, Hybrid (Flash/SRAM), and Antifuse-based FPGAs. Different flavors of these devices are provides by companies like Achronix, Altera, Lattice Semiconductor, Microsemi (was Actel), SiliconBlue, Tabula, and Xilinx. When it comes to counting FPGA design starts (and remembering that we have yet to define just what we mean by “design start”), I personally would include FPGA designs based on any of these technology types.
The vast majority of FPGAs would be classed as digital (let’s not get side-tracked by the analog portions of things like PLLs and the PHY portions of SerDes interfaces). But what about devices like the Fusion and SmartFusion mixed-signal FPGA families from Microsemi? In addition to traditional programmable digital FPGA fabric, these little rascals also include programmable analog fabric (SmartFusion devices also boast hard ARM Cortex-M3 microcontroller cores). This is a bit of a poser, and you may not agree with me, but for my part I would also include designs based on these devices in the count of FPGA design starts.
On the other hand, I personally would not include Customer Specific Standard Part (CSSP) components from QuickLogic or Programmable SoC (PSoC) chips from Cypress. Not that there’s anything wrong with either of these device families, you understand, it’s just that my gut-feel is to not include them under the umbrella of “FPGA design starts.”
What does the term ASIC encompass?
Generally speaking, an Application-Specific Integrated Circuit (ASIC)
is a component that is designed by and/or used by a single company in a specific system. By comparison, an Application-Specific Standard Product (ASSP)
is a more general-purpose device that is (typically) created by an Integrated Device Manufacturer (IDM)
using ASIC tools and technologies, but that is intended for use by multiple design houses and for deployment in multiple systems.
(Note the use of “typically” in the previous sentence. The reason for my employing “weasel-words” like this is that there are a multitude of alternative scenarios, so this helps prevent someone saying: “But what about…?”
And we should always remember the ancient Incan proverb: “Eagles may soar, but weasels rarely get sucked into jet engines!”
– words that are as true today as when they were first chanted deep in the mists of time [grin].)
But we digress… Some ASICs and ASSPs are purely digital (a digital designer’s knee-jerk reaction is to always assume “digital” when he or she hears the word ASIC), others are purely analog, and some include both digital and analog functionality.
The term System-on-Chip (SoC)
is typically used to refer to a digital – or predominantly digital – ASIC or ASSP that acts as an entire subsystem including a microprocessor or microcontroller, memory, peripherals, custom logic, and so forth.
For the purposes of these discussions, we will understand the term ASIC to encompass ASSPs and SoCs. Also for the purposes of these discussions, we will consider ASIC design starts only in the context of devices that are either purely digital or that are predominantly digital with some analog and/or mixed-signal content (How much is “some”? You tell me).
What is an ASIC “Design Start”?
This is the sort of thing you don’t really consider until you start to write an article like this. Suppose a company gathers a team of engineers together to develop a new ASIC. Let’s assume that the team commences work on the architectural specification, realizes that they can’t achieve their goals in terms of power, performance, time-to-market, and/or cost, and terminates the project. Does this count as a design start? Personally I would say “No”
(but what do I know?).
How about if the team goes so far as to create a fully-functional virtual prototype, but then the company “pulls the plug” on the project. Does this count as a design start? I guess I’m sitting on the fence with this one.
Or suppose the team captures the entire design in RTL. Perhaps they go so far as to create a fully-functional FPGA-based prototype. Or maybe they make it all the way to GDSII tape-out. Possibly they even go so far as to receive prototype silicon in their sweaty hands… and then the project is cancelled (bummer). Personally I would say that all of these cases count as legitimate design starts.
Let’s take things a little further. How about when a company creates an ASIC, then a year or so later they re-spin the design to have slightly different functionality. Does the new version count as a new design start? (I would say “Yes”
or maybe “Maybe”
.) And what about the concept of “platform design,” in which a single base design is used to spawn a number of derivative designs – should each of these derivatives be counted as design starts in their own right?
Perhaps a more relevant question might be: “Why are we waffling on about ‘Design Starts’ in the first place?” Aren’t we really concerned only with ASIC designs that actually see the light of day and appear in real products “on the street”? In fact, now that I come to think about it, aren’t we actually interested in knowing both the number of successful chip designs AND the quantity of each type of chip that ships?
I don’t have an answer for this one, but – given a choice – what I personally would really like to see would be (a) the number of design starts (however we decide to define that as discussed above), (b) the number of design starts that fail at different stages in the development process, (c) the number of designs that that make it all the way into production, and (d) the quantity of each type of chip that ships.
Furthermore, I’d like to see all of this information presented retroactively on a year-by-year basis starting from say 1980 to the present day and also extrapolated for the forthcoming ten years. Surely this isn’t too much to ask, is it (grin)?
What is an FPGA “Design Start”?
If anything this is trickier than defining an ASIC design start – not the least that FPGAs may be used to prototype ASIC designs. Let’s start by considering an FPGA design that is actually intended for deployment as an FPGA. In this case, some of the questions we had for ASICs still apply; for example, does a project that is cancelled at the architectural stage still qualify as a design start? What about a project that makes it all the way to a full RTL description before being cancelled?
Suppose a board has multiple FPGAs, each of which is created by a separate team to perform a distinct function. Presumably each of these FPGAs should qualify as an independent design start. But how about a single design that is partitioned across multiple FPGAs – does this count as a single design start or as multiple design starts?
Or what about the case where we are using an FPGA to prototype an ASIC? Ultimately, the ASIC will be deployed and the FPGA will end up in a desk drawer (or wherever). So does this FPGA qualify as a design start? And if it does, then what about the case where multiple FPGAs are used to prototype a single ASIC – do each of these FPGAs count as individual design starts?
How about an FPGA that is used to prototype an ASIC, then ends up in a desk drawer for a few months, then is used to prototype another ASIC, then returns to the desk drawer, and then is used to implement yet another design that is actually deployed in the form of an FPGA. Does this count as one, two, or three design starts?
I don’t know about you, but my head hurts!
The problem is that, out of all the times I’ve seen articles saying something like “There were 90,000 FPGA design starts in 2010”
(and don’t forget that I’m just making this number up), I’ve never seen one that actually qualifies what they mean by the term “design start.” After writing this article I think I know why... because no one has a clue what a “design start” actually is.
How does anyone know anything?
This is where we get down to the nitty-gritty. When someone says something like “In 2010 there were 2,500 ASIC design starts versus 90,000 FPGA design starts”
(and, once again, I’m just pulling these numbers out of thin air), where do these values actually come from?
In the case of ASICs, I suppose that it would be possible to gather data from the foundries as to the number of different chip types that are actually manufactured – also the quantities of each chip type that are produced. But what about “design starts”? The only way to obtain this data would be to query every system design house on the planet as to the number of ASIC designs they started and cancelled. Even if they felt moved to give you an honest answer (keeping in mind that no one likes to admit making mistakes), they may simply not keep rigorous track of the “ones that got away.”
In reality, it would be impractical to query every system design house on the planet. A more realistic approach would be for an analyst to query a select few design houses – estimate the total number of design houses – and extrapolate (“guesstimate”) the number of design starts. (I wonder what the margin of error might be.)
What about FPGAs? Determining the number of design starts for these little scamps is even more problematical. For example, I wouldn’t even know how to go about guesstimating the number of FPGA design houses – how many “two guys in a garage” type operations do you think there might be out there? And if someone orders 1,000 FPGAs, how do we know if this equates to a single design start that ended up shipping ~1,000 parts or to ten design starts that each ended up shipping ~100 parts?
So where do FPGA design start numbers actually come from? Obviously it is in the interest of the FPGA vendors to boast a large number of design starts (and to emphasize how ASIC design starts are falling). But do the FPGA design start numbers come from the FPGA vendors themselves or from some outside party?
As an aside, I was once chatting to a friend at a certain FPGA company (both my friend and the company shall remain nameless to protect the innocent) about some other data I was trying to track down. My friend told me that they never provided this sort of data themselves, but recommended that I contact a certain analyst. However, my friend also cautioned me that the data from this analyst was not typically of the highest quality. When I asked why, my friend responded with a wry smile saying: “Because we don’t give him very accurate information!”
(You either have to laugh or cry.)
In reality, some FPGA vendors guesstimate this data themselves, starting with their knowledge of their own customers and then extrapolating things based on their understanding of the entire market. Alternatively, some FPGA vendors use reports generated by independent analysts who dedicate ferocious amounts of time to gathering and collating this information.
One such hero is Rich Wawrzyniak (firstname.lastname@example.org
), who is the Senior Market Analyst for ASICs and SoCs at Semico Research Corporation (www.semico.com
). One reason Rich also tracks FPGA design starts is because FPGAs are one of the most often used methods of testing or proving out the different types of third-party Semiconductor Intellectual Property (SIP)
blocks that are used in ASIC designs. As Rich says: “The use of FPGAs in this area has become of great importance to every company that designs SoCs of every possible type. Semico also tracks and publishes research on the SoC market and on the SIP market. So if one wanted to be able to accurately gauge the relative health and activity levels in all these markets, having estimates of FPGA design starts – among other metrics gathered about the semiconductor industry – becomes pretty important. Efforts in these areas yield data that is highly useful to many types of companies in making decisions about their future directions and activities.”
The bottom line is that Rich spends countless hours wrestling with questions pertaining to what should be classed as ASIC and FPGA design starts and how we go about counting (or estimating) the number of such design starts. Rich then writes detailed reports comprising hundreds of pages explaining everything in terms we can all understand.
At least, I assume that these reports are presented in terms we can all understand – I haven’t actually been fortunate enough to see one (hint, hint). The sad truth is that this sort of research requires a lot of time and effort, so the ensuing reports aren’t cheap (by my standards) and I cannot afford to purchase them. But I am assured (by Rich) that they are well worth the money (grin).
Well, I think I’ve waffled on enough for now, but if anyone has any information pertaining to any of the topics presented in this article, please feel free to drop me a line at max@CliveMaxfield.com
But wait, there’s more,
because before I posted this article I bounced it off Rich to make sure that I’d covered all of the bases (which, of course, I had [grin]). In addition to adding a few nuggets of knowledge, Rich also said the following:
Max, I’m not sure you want to go into this next part, but I’m going to lay it out here. Many articles have been written and presentations given that put forth the view that the number of ASIC design starts has dropped and is continuing to drop. This is probably true, but it is important to make a distinction here between ASIC Design STARTs and ASIC Designs.
Given all the difficulties the semiconductor market has experienced over the last ten years: 9/11, over-supply and under-supply in the markets, escalating design costs and rising device complexity, financial meltdowns, increasing pressure to integrate functionality into ever smaller envelopes, and anything else that was even slightly negative, it is not too surprising to find that first-time design starts have been reduced. HOWEVER, this is not the whole story, especially in the SoC market.
If nothing else, the semiconductor market is highly adaptive in dealing with specific problems and situations in the markets it serves. If design costs for complex SoCs are shooting through the roof, well then, raise the roof! The way this has been done is to start with a master SoC design and then create other family members by doing derivative designs off of the original master design. In this way the designing company can have more solutions for an incremental increase in cost over the initial, high-cost, design. Adapting to the market conditions and circumstances – a highly innovative solution!
So if one were to step back and ask what the health was of the ASIC-SoC market today, some schools of thought would say the health was poor because the number of first-time SoC Design starts was flat to down. Semico would say that while the number of first-time efforts is flat to down, the number of derivative SoC designs is up and continues to increase year to year. Which view is right?
If you only want to consider first time efforts as being true examples of the state of the art in ASIC Design today, then the ASIC Design numbers are going down and the industry is in big trouble. In fact you could postulate a day, given the current rate of decline, that ASIC Design activity will cease at some point in the future. There cannot be a more incorrect view of the market.
This is especially true when taking into account the level of derivative SoC design activity. This activity is representative of the innovative, can-do spirit found in the semiconductor market. To disallow this activity as valid paints the wrong picture and gives an incorrect impression of the market as a whole.
Semico takes that view that, while it is nice to know the number of first-time ASIC Design start efforts, one needs to consider the total level of effort needed to sustain the very robust worldwide electronics market. Not considering the derivative SoC designs as part of this effort it is like missing the forest for the trees.
To some extent this is also why tracking FPGA design starts is important – the level of activity here can give a partial read on how many designers are looking to refresh their silicon architectures. This is usually better tracked by looking at first-time ASIC Design starts to give an indication of what people are thinking. However, with the financial unpleasantness of late 2008 and early 2009, architectural refreshes of complex SoCs pretty much came to a halt, with first time SoC Designs being flat to down for 3-4 years in a row. One of the best ways for designers to continue to test out and prove out next generation architectures is to use FPGAs as their testing vehicle. This activity is definitely up and sets the stage for a concerted effort by designers to start putting new architectural solutions into the market over the new two years. This is definitely a good trend in the semiconductor market, but it requires companies to take a risk of some type in order to accomplish. A sudden switch back to being risk-adverse will not be a good trend in the market.
From all Semico can see in this area, it seems design activity continues to ramp up and will not change unless economic conditions markedly deteriorate from current levels. We think things will continue to improve over the short term. This is another reason to keep track of metrics like ASIC and FPGA design starts and like conditions in the overall SIP market. All of these areas impact the entire semiconductor supply chain and, to a large degree, set the direction for the entire semiconductor market over the short to near term.
Well, of course, Rich makes some very good points here. All of this goes to reemphasize the fact that calculating the various numbers of design starts is a non-trivial task. And it also makes me want to lay my hands on those Semico reports – I’ll have to start saving (grin).
About the author
Clive (Max) Maxfield is founder, president, consultant, and chief bottle-washer at Maxfield High-Tech Consulting (www.CliveMaxfield.com
). He is also editor of the EE Times Programmable Logic Designline website (www.eetimes.com/design/programmable-logic
). Max is the author and co-author of a number of books, including Bebop to the Boolean Boogie (An Unconventional Guide to Electronics), The Design Warrior’s Guide to FPGAs, and How Computers Do Math. Max can be contacted at max@CliveMaxfield.com