A new device is invented based on a dual metal floating gate structure that can be employed as a unified memory, permitting combined dynamic and nonvolatile storage in the same device. Both memory operations are clearly differentiated by the applied control gate bias and the device can be converted quickly between the two states by applying appropriate voltages. In addition, it allows dynamic operation while being in a nonvolatile charged state. Thus, it can operate as a 2-bit device. Device simulations have shown that it can be scaled down to the 16 nm node.
The device operates as a nonvolatile memory by applying voltage envelopes on the order of 8-10 V and 10-100 μs on the control gate, CGate, which enables charge transfer from the channel through the tunnel oxide ox1 as in traditional floating gate devices and results in a positive threshold voltage shift ΔVT of the device.
For the dynamic memory operation, a low control gate voltage in the range of 4-5 V enables very fast charge transfer on the order of 50 ns through ox2 between the floating gate pair. This charge redistribution results in a slight negative ΔVT in the range of -0.3 V to -0.4 V. The bit stored in the dynamic mode does require refresh. In order to maintain a slight ΔVT of less than -0.1 V, a quick refresh pulse is required to bring ΔVT back to higher negative voltages. The refresh rate may be on the order of 300 ms at room temperature.
A first generation test device has been fabricated that demonstrates both dynamic and nonvolatile memory operation in a single device. The device can potentially be built with high write cycle endurance in the dynamic memory domain by using direct tunneling rather than Fowler-Nordheim tunneling or hot carrier injection. The floating gates may be comprised of metal nanocrystals to further improve endurance.
This device may have a dramatic impact on the power consumption and resiliency of computers. It could enable instant-on computers where the computer can switch quickly between active mode and hibernation on a row-by-row basis. When parts of the memory are not changing, rows, or even entire blocks can be transferred to non-volatile storage without any penalty in read performance. Doing this eliminates the need for refresh, a large percentage of the power consumption in DRAMs, especially in applications requiring few memory writes. Another application is checkpoint storage in fault tolerant computers. Each checkpoint can be stored internal to the memory, thus avoiding the consumption of memory and disk bus cycles. In each application, dynamic operation can continue while a bit is stored in the non-volatile mode.
A memory array utilizing these dual floating gate devices has been designed, which resembles a NOR Flash architecture. It is intended to replace a DRAM with a combined memory. The array may switch to a hibernate mode in ~30 ms, assuming 1024 rows in each memory bank. A switch from a hibernate mode to the active mode takes ~14 ms. Compared to a conventional DRAM, the read-mode is fast and non-destructive. Depending on the number of rows in the array, the clock frequency may be in the order of 230 MHz for 1024 rows per memory bank or 1.61 GHz for 64 rows per bank on the 45 nm technology node. In the read mode the word line is biased with 1.2 V, comparable to tomorrow’s DRAM, and scales with next generation technologies. The dynamic write voltage is relatively high compared to DRAM but is compensated by 4-5x longer between refresh periods.