It should be widely appreciated that implementation of new LTE and LTE-Advanced mobile communications standards is only made practical by advances in semiconductor manufacturing technology. Moore’s law makes possible the millions of logic gates and Megabytes of memory required to run 4G in a baseband processor chip that is small enough, low enough in cost and miserly enough in energy consumption to be used in a mobile handset or portable tablet computer.
However, the processing demand from LTE is enormous and so the very latest DSP and general-purpose processor architectures must be designed to take advantage of the semiconductor capability. This is the case with the latest real-time embedded processor from ARM, the Cortex-R7 processor, which has an extremely powerful superscalar architecture capable of delivering over 1,500 Dhrystone MIPS from a square millimeter of 40 nm silicon, when running at a clock frequency of 600 MHz.
Besides extreme performance, the Cortex- R7 processor has a number of key system integration features that make it highly suitable for LTE baseband protocol stack processing. These baseband software protocols are layered with layer-1 driving the DSP modem hardware, layer-2 managing the radio connection and layer- 3 making the call, identifying the handset to the network and dealing with location and mobility.
This is highly complex software that is tightly integrated with the DSP modem hardware, and, for high data rate LTE and LTE-Advanced, it typically requires a dual core Cortex-R7 processor configuration if it is to run efficiently.
In fact, such dual processor configurations are already common in today’s 3G and HSPA mobiles, and almost always running on either ARM11 or ARM Cortex-R4 processors.
Hardware integration using real-time interrupts
Integration with the modem hardware is achieved through the use of many real-time interrupts; over 50 in many designs. These interrupts arrive from the modem at high frequencies (for example, at LTE symbol rate of 14 interrupts per millisecond) and must be rapidly processed in the Cortex-R7 processor to manage the modem and the radio as they constantly adapt to changing signal conditions and download or upload data at a high rate. Many small fragments of data flow in and out of the system and these must be error checked, re-transmitted if required and assembled or disassembled to and from finished IP packets that pass in and out of the user’s applications.
Simultaneous data streams may be present for audio, video and data communications together with control data for the handset’s interface to the cellular network. This is a hugely complex and high performance processing task. An LTE baseband modem and processing system is illustrated in figure 1.
Fig 1: Illustrative LTE baseband system.
Various hardware blocks are identified for the LTE standard’s Forward Error Correction (turbo code), Hybrid Automated Resend reQuest (HARQ) and RObust Header Compression and Ciphering (RoHC) for security. There is also a Scatter-Gather DMA Controller that keeps track of all the fragments of data flowing in and out of the system. The modem is responsible for OFDMA coding and decoding of the radio signal and is implemented using DSPs or a Vector Signal processor, VSP.
The system illustrated uses a dual core Cortex-R7 processor for layer-2 and layer-3 protocol processing with much of the layer- 1 work being done by sequencers and state machines within the modem hardware. However, some layer-1 tasks will also be performed by software in the Cortex-R7 processor. This system demonstrates a number of key features in the architecture of the Cortex-R7 processor, designed to ease practical implementations of an LTE baseband system.