Relieving the pain of parasitic extraction
The future is here: phone, web browser, email, photo and video, all in one device at your finger tips, simultaneously. The evolution of IC design is in part driven by the demand for more memory with higher performance. Advanced process technologies enable more functionality, higher performance, and portability in chip design through smaller device sizes (Figure 1). These innovations pose interesting design challenges, which include new parasitic extraction issues that are affecting nanometer memory designs.
Figure 1: Minimum device feature size trends.
Embedded memories already dominate most of an SoC’s die area. The ITRS roadmap [1
] predicts that memory functions—the number of bits on a single chip—will double every two years. Performance is the key requirement for leading-edge memory design. Memories must meet exacting specifications for fast data transfer and low power consumption.
Areas of concern for memory design at nanometer nodes include storage capacitance with reduced feature size, low resistance for bit and word lines to ensure desired speed, improved bit density, and lower production cost [1
]. Higher densities increase the interactions between interconnect lines, as well as those between interconnects and devices. New device and interconnect design techniques used at 28nm introduce more complex coupling effects that are difficult to extract accurately. Geometries are becoming more three dimensional in structure, and circuits are more sensitive to 3D parasitic effects.
Transistor-level simulation including very accurate parasitic effects is critical to the memory design process to help designers converge on an optimal design that has a high certainty of meeting targeted specifications, without costly overdesign.
More accurate solutions are required that do not increase cycle time and that fit into existing design flows. New 3D parasitic extraction technology delivers attofarad accuracy as well as high performance and capacity, at all stages of memory design, from bit cell design to full chip sign-off, ensuring a robust design that will work to specification when it is manufactured.