EETimes recently carried a report  of new work reporting new low power phase change memory (PCM) devices. Workers at University of Illinois Urbana-Champaign have reported their results for phase change memory (PCM) devices formed by creating narrow 20–30nm gaps in 3nm diameter carbon nano-tubes (CNTs) and opened some new directions for further investigation .
While the authors  comment optimistically on fabricating low power PCMs, there is no discussion of current density. They describe their “best” results, obtained from PCM devices with set/rest currents of 1uA/5uA respectively with 3V across a 20-30nm gap and their stated carbon nano-tube diameter as 3nm. Assuming that the contact is solid planar, the contact current density calculates as
J = 7 x 10+7 Amps/sq-cm.
The authors  report higher values of reset currents 8uA, for what as described as not their “best” devices, for unspecified reasons, increasing the calculated current density value (J) to ~1 x 10+8 A/sq-cm. If the electrodes are truly tubular, as illustrated in Figure 1 (a) and the notional contact is as shown, the contact current density is likely to exceed this value. Even if the region of molten chalcogenide penetrates into and around the end of the CNT tube during reset, enlarging the contact area as illustrated in Figure1, (b), the total contact area will still involve only a few hundred atoms.
Figure 1: Diagram showing two cutaway views of one electrode of a carbon nanotube (CNT- PCM, (a) the notional contact area of an annulus of atoms,(b) cutaway section CNT-PCM during reset.
Atomic force microscope (AFM) evidence from  appears to show a flat spherical shaped region of active material equal to about 2 to 3 diameters, approximately the gap width. This suggests the molten region may not extend very far into the CNT. As well as the active region, the calculated levels of current density will have a deleterious effect on other components in an array and that is already one of the serious and ongoing PCM problems.
With respect to current density, there is now good evidence , summarized by this author in  that during reset the molten GST material acts like an electrochemical cell (plating bath) and it is that process that accounts for element separation, composition change and eventual failure. Therefore an argument might be made that an emphasis on current density as the “villain in the piece” for the memory device, especially for the very small contact area of the CNT-PCM devices might be misplaced. Current density is in effect the signature of the presence of the “electrochemical cell” plating voltage, with the former necessary to maintain a very small volume of chalcogenide in a molten state.
Ron Neale continues to track the progress and developments in PCM, so I asked him to sum up the activity for the first quarter this year. Please feel free to discuss, debate, and speculate in the comments section.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.