The authors  suggest that they were able to get 200 write/erase cycles from the carbon nano-tube devices. Their write/erase cycle time set/reset was 150/50ns. Add to that some read verify time it would not take long to reach 1000+ cycles. So, it must be assumed 200 cycles was somewhere close to a maximum.
What would be more important to know is was the predominant failure on state or off state? One of the key pieces of information provided that might be significant to the observed write/erase lifetime is the fact that all devices were reported by  as having very similar “on” state resistance. An explanation of this might be the domination of the total resistance of the “on” state by the spreading resistance of the very small contact area between the two ends of the 3nm CNTs and the crystallized region. Examination of the micrographs  suggests that the active region is of a flat spherical form.
It is worth comparing the write/erase lifetime reported by  with those specified for two PCM devices that are available as products in array form, they are what might be described as “reality” lifetime numbers. In Figure 2, the latest results for the CNT devices have been plotted with the array “reality” numbers as a function of the lithographic node. With the cautionary note that two point extrapolation is dangerous territory, even more dangerous on logarithmic plots, a line from the array points extrapolates to a point close to the new results, covering a range of 3 decades.
Figure 2: Comparison of PCM w/e lifetime of CNT-PCM with “reality” values from fully intergrated arrays.
In Figure 2, the dashed error bar allows for some possible improvement in CNT w/e lifetime. That improvement may not be achievable for reasons to be discussed next.
It has always been possible to obtain impressive write/erase lifetimes for a single PCM device, especially if multiple reset attempts are allowed (a situation that can also inadvertently occur if the device under test is allowed to free run and a read verify operation is only carried out at intermittent intervals).
There are many examples in the literature where larger area PMC devices have on/off resistance values that are very constant in the early part of write/erase lifetime. Later on, the values become more variable, prior to failure. One good early example of this for a modern-era PCM device can be found in .
In Figure 3, for illustration purposes, a large number of observations from different sources have been combined. The off state resistance in Figure 3 has two characteristics, initially zone “A”, a very stable region, usually of the order 103 to 104 write/erase cycles. This is followed by a region where the off state resistance fluctuates to a larger extent in a random manner, so the device does not move out of acceptable tolerance. The on state has a similar characteristic over a much smaller resistance range.
Figure 3: The average write/erase resistance characteristics from a large number of devices illustrating two typical zones.
On occasion the write/erase characteristics in region zone “A” are observed to display a discontinuity, after which region “A” type characteristics resume. Sometimes short bursts of region “A” characteristics are observed in region B.
This author’s view is these characteristics are the result of the movement of the active region of the PCM and its point of contact with respect to the electrode(s). In zone “B” of Figure 3, the device could be said to be carrying out a self-repair. This would suggest that from whatever the cause a 1000 to 10,000 write/erase cycles might represent some fundamental limit for a single location. Where write/erase lifetimes beyond those values are reported, they are in effect the combined results of a series of different devices formed by self-repair or reforming of the same active material in the same PCM structure. Unless the mechanisms that are responsible for the zone “B” characteristics in Figure 3 are clearly understood, there is an inherent reliability risk, even though the devices are within operating tolerances.
Readers should be clear, a PCM device that is still operating after being subject to 109 write/erase operations may not be the equal of a device that has operated reliably for 109 write/erase cycles, with read verify during and after each write/erase operation. Ref  for a constrained 50 to 80nm PCM device is shown to exhibit fairly constant on/off state resistance values up to 109 write/erase cycles, with what appears to be a small zone “A” transition jump at about 103 write/erase cycles. After that, the extended write/erase lifetime is only reported at decade intervals.
The problem is, when combined in arrays, the “reality” value of write/erase lifetime number cited is always much lower as is indicated in Figure 2. In that respect, over time little has changed, the very early data sheets (ca1970) for very small PCM arrays indicated a write/erase lifetime of 600 cycles, accompanied by some multi-pulse recovery (repair) advice, while at the same time individual devices could withstand in excess of 106 write/erase cycle operation cycles and still be operating.
The reported write/erase lifetimes for the 3nm CNT devices of  only showed zone “A” characteristics. The problem might be that with a 3nm diameter CNT electrode the conducting region cannot move, given the same set and reset pulse conditions and therefore the device fails after 200 write/erase cycles of single structure operation. This is a fundamental problem with its root cause in the current density and electric field across the fine contact point, discussed here in an earlier paragraph. Other causes might be the manner in which the sputtered GST deposits on the CNT. Does the sputter deposited material penetrate the CNT to form a homogeneous GST core region? That is, do sputtered atoms pass though the rings of carbon and the sidewalls of the tube, or does the CNT remain hollow or contain voids?
For the future of PCM, it would be important that U of I-U receives additional funding to establish the cause of the 200 write/erase cycle lifetime, or even increase it. If the short write/erase lifetime is of a fundamental nature, caused by elemental separation, and the inability of the active area contact to adjust or move. If that is so, there would appear to be little point in developing methods of fabrication for CNT based PCMs, or any other metals for that matter, leastways for PCM applications. (From this quarter we suggest two useful write/erase lifetime experiments would be PCMs with either MWCNTs or larger diameter CNT electrode tubes.)
Ron Neale continues to track the progress and developments in PCM, so I asked him to sum up the activity for the first quarter this year. Please feel free to discuss, debate, and speculate in the comments section.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.