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How to achieve quality assurance for your electronic designs

4/4/2011 03:22 PM EDT
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CamilleK
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re: How to achieve quality assurance for your electronic designs
CamilleK   4/7/2011 5:10:44 AM
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Automation of best practices and continuous tracking and improvement have always been near and dear to my definition of disciplined design. Donald Reinertsen famously spoke of Managing the Design Factory. With accelerating schedules and with increasing complexity, it is becoming important to mostly handle exceptions and leave the rules to be auto-tracked with the 'sensor/probes approach' Satin is implementing. I view this as re-using methods and methodology insuring repeatability of 'criteria of goodness' with easily identifiable 'care-abouts', critical behavior, performance monitors, alerts, comparative metrics and a host of quality and functionality trackers. By also providing standard template-like probes, the wisdom of design practice past feeds into evolved learning that tracks the important stuff identified over a history of prior uses or experiences and if a unique probe is needed, it can be easily folded or added while remembering the baseline behavior. Evolution and genetic signature come to mind. To add to Piyush's astute PLM comment, I echo the need for Design/EDA to intelligently mine data deployed a while back by the finance/IT industries. I like what has been done here and let us stay in the fast VIP lanes with high RPM Quality engines.

JB_DMAP
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re: How to achieve quality assurance for your electronic designs
JB_DMAP   4/6/2011 5:32:46 PM
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The concepts developed in this article should sound like a pleasant aria for all teams involved in an avionic design, especially when you must comply with the dread DO-254!

Piyush Sancheti
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re: How to achieve quality assurance for your electronic designs
Piyush Sancheti   4/5/2011 12:08:45 AM
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Max - a very good and timely article on this topic. More and more design managers and execs are looking for objective metrics to manage the chip lifecycle from spec to silicon. The discrete manufacturing industry has been using PLM (product lifecycle management) tools for many years, and it's time that the EDA industry steps up to deliver similar solutions to help chip desinger manage the increasing complex, expensive, and compressed chip development life cycle. VIP Lane is definitely a step in the right direction. A Dashboard with objective pass/fail metrics data-mined from the user's design verification and implementation tools makes good sense, and maximizes your investment in EDA tools. In fact we have happy customers who are using results from Atrenta's SpyGlass platform (for RTL analysis & optimization) displayed in VIP Lane Dashboard. If your are design manager, you ought to take a look at this stuff. Piyush Sancheti Atrenta Inc.

Max The Magnificent
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re: How to achieve quality assurance for your electronic designs
Max The Magnificent   4/4/2011 3:43:35 PM
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This is one of those things where I say to myself "I wish I'd thought of that!"

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