PCI Express (PCIe) has successfully penetrated business-focused market segments -- graphics, storage, servers, communications, and embedded systems – helped immensely by the ubiquity of PCIe interfaces on everything from high-end CPUs from Intel; GPUs from nVidia: embedded processors from Freescale, AMCC, and Cavium; and consumer products from Atheros, Marvell, Broadcom, Infineon, and Conexant.
Wi-Fi modules, set-top boxes, cable modems and home gateways now feature PCIe, and both the volume and number of product types are growing by leaps and bounds. This has helped to drive the presence of PCIe in all market segments ranging from graphics, servers, storage, communications and consumer products, to improve the ecosystem and to lower costs for customers, making it a win-win for all involved.
What has not been well known but has emerged recently is the presence of the PCIe interface on DSPs from Texas Instruments, Freescale, and LSI. In the past DSPs had either proprietary interfaces or Serial RapidIO (sRIO), but now DSPs have PCIe interface as well, offering designers more options for connectivity, and at lower price. This is especially important given the penetration of PCIe into rapidly evolving product categories, such as wireless base stations, video surveillance systems, video communications, medical and biological imaging, home A/V equipment, and digital video recorder/network video (DVR/NVR) boxes – all markets that continue to be bastions of DSPs.
This article will look at this development with examples of usage models and how it benefits the DSP makers, designers and end users - the entire ecosystem. This article will also look at the options designers have in PCIe interconnect and help them maximize both performance and power efficiency of DSP designs. Additionally, it will illustrate how that efficiency is achieved by taking advantage of PCIe switches’ flexible ports and lanes, small packages and unique ability to fan out to a number of endpoints.
From its debut of actual silicon in 2004, PCIe has penetrated every market segment, not the least of them consumer electronics, along with graphics cards, add-in cards and motherboards. Yet even after all that success, there has been one major portion of the market segment that to date hasn’t adopted PCIe – wireless base stations. This was primarily because the available DSPs used were either sRIO-based or the manufacturers used their own ASICs with proprietary buses.
All that’s changing now, primarily because the DSP vendors have realized that the market is demanding more connectivity options. Designers need a standard interface that is both inexpensive and widely adopted by thousands of customers, with a solid ecosystem that guarantees multiple sources for any device.
Also, DSP vendors now don’t have to add multiple interfaces to satisfy their varied customer base; they can now add one lane of PCIe 2.0 (Gen 2) at 5Gbps and save significant space by removing several pins of any proprietary interface on their packages, enabling them to offer more cost- and function-optimized devices.
Since PCIe has been around for more than seven years, the cost structures are now at a point where it makes economic sense to utilize this interface. Furthermore, the ecosystem is huge, which makes connecting to PCIe endpoints extremely easy. Last but not the least is the emergence of endpoints based on the latest complementary interconnect technologies such as USB 3.0, whose bandwidth requirements are supported by PCIe Gen 2 PCIe.
Most of the DSPs have only two PCIe lanes configured as 1 x2 PCIe port, a PCIe switch optimized for this market ensures connectivity to the large number of endpoints. Let’s take a look at some of the usage models in these applications driving the need for a PCIe switch.
Fig 1: Digital video recorder/network video recorder.
In DVR/NVR usage model illustrated in figure 1, the single x1 interface from the DSP is being fanned-out to connect to several endpoints, which have PCIe native. If the PCIe interface did not exist on the DSP, then the designers would have to use proprietary interfaces to connect these endpoints, which would have been a headache to implement on the FPGA and ASIC, not to mention in the video encoder.