NOR Flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product. NAND Flash devices have become a viable alternative in systems where read latency and data integrity are not critical device characteristics. This paper describes NOR’s current trajectories and operational characteristics that will enable usage in future applications.
Process shrinks allow for extended product life cycles
Over the past decade the pace of density growth has continued at a remarkable rate (Figure 1). Density growth will continue into the future. In 2011 we will see the introduction of a 4Gb NOR device and the next generation process node (45nm) will be released to production in 2012. Work has already begun on the follow-up node at 32nm to continue the process development roadmap.
FIGURE 1: Spansion’s NOR Flash Density Growth over the Last Ten Years
NOR manufacturers have historically been aggressive in applying new process technologies not only to the highest density devices but also to reduce the die sizes of lower density legacy products. Spansion’s 65nm process is not only used for the highest density 2Gb (and upcoming 4Gb) products but is also being used to shrink products between 64Mb and 1Gb. The smaller die sizes resulting from the continued application of new process nodes extends the length of time that a product remains commercially viable. While the 1Mb Async NOR product (AM29F010B) referenced in Figure 2 uses an older process node (320nm), it should be noted that the device is compatible with the much older AMD AM29F010 that was released to production in 1992 (using an even older process node). NOR’s extended product life cycle and breadth of available densities is unique in the memory industry.
FIGURE 2: Available Densities of Candidate Memories
The longer product life cycles are also due to reduced pressure for a typical NOR application to migrate to the highest density node. Overall, NOR’s wide range of applications have a much broader distribution of density usage than NAND applications. NOR applications tend to vary widely in density requirements and migrate to the next higher density node rather than jumping to the highest density device. The bulk of NOR applications do not migrate to a leading edge density as compared to NAND applications that tend to rapidly migrate toward the highest available device density. NAND’s focus on leading edge densities often comes at the expense of lower density products (using older process nodes) that tend to become obsolete after relatively short life cycles.
One significant NOR usage change is the continuing proliferation of high density SPI. As a NVM product catagory, NOR revenue is more than adequate to fund next generation process development and new product catagories.
I tried to use a typical usage case scenarios. As tb1 mentions x16 NAND is getting hard to find and commands a significant price premium. Note that even if the NAND transfer time were eliminated altogether the NOR:NAND comparision would be 50:1.
I think the major flaw in that argument is that NAND and NOR are typically used for very different purposes and there are very few typical user scenarios for both beyond holding boot code/data.
Trying to compare them is like trying to compare a Ford F250 with a Porche.
NAND is prefered for general r/w file system usage - for which NOR is pretty terrible.
NOR is prefered for boot code and data, but many systems are dropping the NOR and using NAND to reduce costs. That slows boot, but is a compromise.
NAND array architecture is fundamentally more efficient (bits/area) than NOR at a given process node. This array efficiency advantage outweighs NOR's smaller peripheral area as densities increase. From a silicon cost perspective NAND will always be less expensive at the highest densities, NOR will always be less expensive at the lowest densities. So from a cost perspective both NOR and NAND will continue to be viable for the foreseeable future.
From a performance perspective both technologies have characteristics that are essential in different applications. (NOR - low latency reads, NAND - fast program/erase rates)
Hi, I'm interested in Flash energy consumption to complete a fair comparison between different technologies (particularly in NOR and NAND Flash, SRAM). This parameter is normally disregarded in books and so on. Please could you give any clue on orders of magnitude of the static consumption (specified as current/power leakage) and dynamic consumption during random read operation. Best regards, Leonardo