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Debugging for antenna issues in copper processes

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docdivakar
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re: Debugging for antenna issues in copper processes
docdivakar   6/27/2011 6:39:29 PM
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@John.Ferguson_#4: thank you for the follow up. I am not aware of any tradeoffs on the number of via's vs. susceptibility to antenna failure (I am not a process guy but do talk to couple of friends who are and hence I am dangerous with half-knowledge!) MP Divakar

John.Ferguson_#4
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re: Debugging for antenna issues in copper processes
John.Ferguson_#4   5/17/2011 8:16:46 PM
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Thank you Dr Divakar, I don't have any data to validate my thinking, but I would expect that the charge that accumulates to a lower level of metal due to the etching of vias in copper should be less than the charge used to actually etch out the interconnect lines themselves as is done in aluminum. This would be worth some further investigation. That said, you remind me of a question I've had. To help address issues associated with copper voiding, via doubling has become a common practice in nanometer IC design. But we know that more vias means greater susceptibility to antenna failure in those same copper processes. I'm curious if anybody has done any analysis on the trade-offs?

docdivakar
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re: Debugging for antenna issues in copper processes
docdivakar   5/12/2011 5:06:31 PM
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Thanks for a good article. I was aware of the charge buildup and the tricks to take care of it at layout. The article clearly explains the differences between Al & Cu on charge buildup which also implies the Cu circuits are inherently more expensive to fabricate because of the additional number of vias needed (not to mention other costs like material cost, dual damascene & process-related differences). Dr. MP Divakar

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