As the speeds of various SerDes interfaces move into the multi-gigabits/sec range, more ASIC chips are being designed to have multiple high speed interfaces such as USB 3.0, PCIE Gen3, DDR3, and others. No longer is package design just a layout exercise or lumped model extraction.
Package design flow
It’s now more important to understand the interaction between the bumps, traces, vias, and solder balls in a flip chip package — or wirebonds, traces, vias, and solderballs in a wirebond package — to optimize the package layout and design before committing to high volume production. Today’s requirement is full 3D electromagnetic simulation (EM) and modeling to optimize the package design for crosstalk, reflection, and insertion loss. The package can no longer be designed “by itself” but has to be designed in conjunction with both the silicon chip and the system board, an approach commonly known as chip-package-board co-design. Let’s look at some important design considerations and an effective high-speed methodology successfully employed for the design of a package with a USB 3.0 interface using 3D EM modeling and simulation.
Flip chip package design example using IE3D for USB 3.0
USB 3.0 is a dual bus architecture that incorporates USB 2.0 plus a super-speed data bus. The super-speed data bus employs differential signals and has a speed of 5 Gbits/sec. One of the initial design goals for the USB 3.0 differential traces is an S11 (reflection loss) parameter of 15 dB or less at 2.5 GHz or higher and a minimum insertion loss S12 of less than 0.5 dB.
Figure 1 shows a four-layer flip chip package to be used as a design example. This design was constructed using the package design software in Mentor Graphics IE3D flow. This example is a BGA package using build-up substrate technology. The vias encompass blind, buried, and through types. Also, via-in-pad technology is used for routing from the flip chip bumps to the inner layers on the BGA package.
Figure 1: Four-layer flip chip package stack up example design
Chip bump coordinates and netlists are generally provided in the form of a Microsoft Excel spreadsheet. The data is read into package design software. A die symbol and a package symbol are created. This is the first step in the package substrate layout. High speed and critical nets are routed first, from solder bump to solder ball.
The layout of the critical nets and high speed nets in the package design software is shown in Figure 2. These high speed nets are routed as differential nets and length matching between the pairs is done within 25 μm. These nets are routed on layer 1. Layer 2 is a ground plane layer, which provides the return path for all the signals, differential as well as single ended.
Figure 2: Top layer layout of the package showing the high-speed nets
Nice article BUT one request: if you refer to numbers in the figure, PLEASE make the figures larger so we can see what they are! The improvement in 15dB point is some what ambiguously pointed to filling the via though I agree it improves marginally. It is the additional ground vias in the return path which is well a known practice in highspeed design.
One thing your article completely ignores: USB 3.0 has higher max current draw, 900mA @5V DC. The corresponding flip chip interconnections and the package substrate designs have to take into account the current density & electromigration effects at the flip chip to substrate interface. So what is supposedly a good signal integrity-verified design does not automatically guarantee a reliable design.
Dr. MP Divakar
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