Breaking News
Design How-To

Overcoming the challenges of formal verification and debug

5/18/2011 01:08 PM EDT
3 comments
NO RATINGS
Page 1 / 2 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Neo10
User Rank
Rookie
re: Overcoming the challenges of formal verification and debug
Neo10   5/19/2011 4:42:51 AM
NO RATINGS
Writing assertions is not a simple task if we really want them to acheive functional coverage. It takes a lot of effort and design insight which accoutns for a major chunk of enineering time for verification. This being the case the problem is this tool is addessing is at a later stage when we have robust assertions and a clean flow using the same, else we end up spending a huge part of our time just addressing the mistakes in ones property description. And we have not even accounted for cases which are prone to race. The problem with deplying assertions widely is that it requires good design and tool knowledge to write one effectively and when that happens you need an even more undertstandable person to debug any failures. So, hmm.. this tool is trying to bidge this gap I suppose, should be interesting.

cdhmanning
User Rank
Rookie
re: Overcoming the challenges of formal verification and debug
cdhmanning   5/19/2011 12:38:57 AM
NO RATINGS
This looks like Test Driven Development (TDD) for VHDL. It makes sense to cross pollinate tools from software development into other areas too.

Luis Sanchez
User Rank
Rookie
re: Overcoming the challenges of formal verification and debug
Luis Sanchez   5/18/2011 9:27:05 PM
NO RATINGS
Great article! very interesting to read about your methodology to study and compare the new approach against the former. The reduction in test time from 36 to 21 hours is a great benefit. This is a field where it will always be necessary to improve and reduce times as time to market may be sometimes crucial.

Top Comments of the Week
August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
5 comments
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Radio
LATEST ARCHIVED BROADCAST
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.
Flash Poll