Most modern electronics require some form of dynamic, random access memory (RAM). By far, the most common today is Stub Series Terminated Logic (SSTL)-driven Double Data Rate (DDR) memory. While DDR memory is very popular for meeting modern electronics demand for large amounts of high-speed memory in a small form-factor, providing power to DDR memory can pose some difficulties.
Conventional logic and I/Os utilize standard system bus voltages; however, DDR memory devices need the precision that can only be obtained with local point of load (POL) regulators. What’s more, two of the five supply voltages are required to reference other voltages for sufficient noise margin. The VDD I/O voltage, VDDQ core and VDDL logic voltages, along with a precision tracking reference, VTTREF and a high-current capable mid-rail termination voltage, VTT, make up the power requirements for a DDR memory solution.
Most DDR memory devices use a common supply for core (VDDQ), I/O (VDD) and logic (VDDL) voltages, commonly combined and referred to as simply VDDQ. Current standards include 2.5V (DDR1 or just DDR), 1.8V (DDR2) and 1.5V (DDR3). DDR4, currently slated for release in 2014, is expected to have a voltage between 1.05 – 1.2V, depending on how far the technology advances before the standard is released.
DDR memory’s VDDQ voltages is the simplest supply rail. With most DDR memory devices allowing three to five percent tolerance, it can be supplied through a variety of POL power solutions. Single chip, “on-board” memory solutions for smaller embedded applications might only require a linear regulator to provide an amp or two of current. Larger multi-chip solutions or small banks of DDR modules typically require several amperes of current and demand a small switch mode regulator to meet efficiency and power dissipation needs. Larger multi-module banks, such as high performance processing systems, large data-logging applications and testers may demand 60 or more amperes of VDDQ current, driving designers to develop processor-core-like, multi-phase power solutions just to meet memory needs.
While VDDQ can typically be supported by a conventional converter, it generally requires pre-bias support and the ability to regulate through high-speed transients as the memory switches states.
There is no defined standard for “pre-bias support”, but it implies that the POL converter providing the VDDQ voltage is designed to prevent sinking current out of the VDDQ supply if there is any voltage already stored on the VDDQ bypass and output capacitors during VDDQ power-up. This is critical, because SSTL logic devices commonly contain parasitic and protection diodes between VDDQ and other supply voltages, which can be damaged if the VDDQ supply sinks current through them during start-up.
Additionally, high speed memory cells switch states rapidly. A memory chip or module may transition from a low intensity sleep state, stand-by or self-refresh state to a highly demanding read-write cycle in just a few clock cycles. This places another strong demand on the POL supply providing the VDDQ voltage. Generally, VDDQ supplies are expected to transition from only 10 percent of their maximum load current to 90 percent in a micro-second or two. Faster, cycle-by-cycle transitions are typically provided by an array of small, local bypass capacitors (near each VDD, VDDQ and VDDL input) to the memory device while a combination of large output capacitors and high-speed control loops provide for sustained mode transitions while meeting the tight accuracy requirements of DDR memory devices.
Where VDDQ is a high current supply that powers the core, I/O and logic of the memory, VTTREF is a very low current, precision reference voltage that provides a threshold between a logic high (1) and a logic low (0) that adapts to changes in the I/O supply voltage. By providing a precision threshold that adapts to the supply voltage, wider noise margins are realized than possible with a fixed threshold and normal variations in termination and drive impedance. Again, specifications vary from device manufacturer to manufacturer, but the most common specification is 0.49x VDDQ to 0.51x VDDQ and only draws tens to hundreds of micro-amperes.
Smaller memory systems using a single to a few ICs will typically use a simple resistor divider, counting on the low leakage currents of the reference input voltages to minimize any variation in the threshold voltage and achieve the two percent tolerance necessary to realize the best possible noise margins.
Larger systems using multiple memory modules, such as standard DIMM modules, will typically elect a less sensitive, active VTTREF solution, such as an operational amplifier (op amp) buffer after the resistor divider or a voltage supplied by a dedicated DDR memory solution (see Figure 1), such as TI’s TPS51116, TPS51100 or TPS51200.
VTTREF should always be locally generated, referencing the VDDQ voltage at the source device to provide the most accurate threshold voltage and widest possible noise margin. That requires the memory’s VTTREF voltage to reference the processor’s VDDQ voltage and the processor’s VTTREF voltage to reference the memory’s VDDQ voltage.
The statement "Any useable system will need to have the outputs terminated" is not true.
If you use a point-to-point memory interface with on board packages, short leads and controlled driving impedance's, parallel termination of data lines may be removed, saving considerable power and relaxing Vtt req's. The address/control bus will of course still need parallel termination for buses wider than one package.
Case 2) Calculating the additional VDD supply to power the I/O function, which is "Iout = 0A" in the datasheet VDDQ current specification. When calculating the additional VDD supply current, one must consider one half of each of the differential pairs because one of the pairs is sourcing current from the I/O supply (VDD) into the termination node while the other is sinking the same current from the termination node to ground. The currents cancel with respect to the termination node (they form a matched resistor divider) but there is still current flowing from VDD to VTT and from VTT to GND through the drivers of the differential pair and that current still needs to be sourced from VDD, even if it doesn't need to be sourced from VTT.
Case 1) Calculated the necessary termination current: When calculating the termination current (current sourced or sunk by the termination supply) Each differential pair is self-canceling since one line of the pair will source current and the other line sink an equal current. Producing a net 0 current.
Let Me See,
There are 2 different cases for reviewing the output current needed.
To calculate the source/sink current at the termination voltage however, the differential pairs alawys cancel as one of the pair sources current into the termination node and the other sinks current from the termination node, generating a net zero-current.
However, to calculate the additional input current on the VDD supply, we need to consider that half of the differential pair strobe-lines will always source current into the termination while the other sinks that current. While these currents cancel from the termination node's point of view, they don't cancel from the I/O Supply.
Thanks for the article. I have a doubt wrt to this statement. "Reviewing the pin assignments of this device, we identify 16 data lines and up to eight differential strobe lines (if used) for a maximum of 20 terminations. We only consider half of the differential pair strobe lines since one is always low while the other is high."
At one point you say a 1 and 0 would cancel out each other and draw no current. but when it comes to DQS/DQSX you are still counting half the number. Aren't they always 10 pair and so one doesn't need to count that current ?
TI also offers switch based VTT solutions in both internal MOSFET and external FET configurations, one is even mentioned in the article. Switched solutions are not always "better" they are different. They offer a small improvement in power consumption at the expense of increased cost, size and component count. For most applications where RMS current on the VTT rail below 1A, switching solutions save very little power. At 1A using DDR2, the savings is a mere 400mW if the switcher is 100% efficient!
The article is based on an Embedded Systems Conference - Silicon Valley 2011 presentation that I gave in May 2011. Since it was a conference paper, I tried to avoid marketing specific reference designs.
The basic design will vary depending on the power levels needs, and currently most reference designs focus on the mid-current levels of 3-10A of VDDQ current & 1-2A of VTT current used by mobile computing solutions. An example of such a solution can be seen in the datasheet for the TPS51116 DDR Power Regulator from Texas Instruments.
Thanx for posting this article. Too many times memory articles focus on the timing of the interface and not on the power issues. This is a very useful overview. Now we just need a good reference design to pull it all together. Anyone know of a good one?
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