Automated physical datapath helps meet custom power, performance and area goals with predictable results and shorter design schedule
Custom datapath designers designing microprocessors, digital signal processors (DSPs) and graphics processors have to meet aggressive Performance Power Area (PPA) targets. They use datapath techniques such as tiling to layout highly regular structures for commonly used building blocks such as adders, multipliers, coders, decoders, etc., used in processor designs. In tiling, the designer partitions specific functions and arranges library cells for those functions into rows and columns. Each cell is placed relative to the other cell; as an example, cell A is on the same row and to the left of cell B and so on. Tiling enables custom layouts that can meet rigorous PPA targets. However, tiling requires a lot of manual work to make sure the structure is regular; the cells are optimal and address multi-mode multi-corner, SI and multi-voltage requirements. Creating and maintaining the optimality of tiling throughout the design flow is time consuming and results in longer design cycles. At the same time, designers designing mobile and multimedia SoCs at 40nm and below are also using processor cores. These “mainstream” designers would like to target that same custom performance but without the penalty of longer design cycles and extensive manual intervention. Additionally, datapath techniques are being extended to design structures such as register banks, clock trees, multiplexers, etc. In summary, mainstream designers need an automated datapath solution that allows them to meet custom design objectives with predictable and shorter design schedules.
What are custom datapath designs?
The logic in digital designs is typically classified into two categories: control blocks and datapath blocks. Control blocks are random in nature and are handled well by standard synthesis and place-and-route tools. Datapath blocks perform Boolean (AND, OR, and XOR) or arithmetic (ADD, SHIFT, and MULTIPLY) operations. In datapath designs, Boolean or arithmetic bitwise data operations are performed in parallel on each bit of a bus. Each operation corresponds to a dedicated function, for example, adder, multiplier, register and multiplexer. Figure 1 shows an example of a datapath block.
Figure 1: Datapath block
Datapath blocks, shown in Figure 1, require regular structures that are not well supported by synthesis and place-and-route tools, as they do not consider the regularity of datapath cells as a cost function. Therefore, designers implement datapath blocks manually by using tiling structures where the blocks are partitioned into dedicated sections on the floorplans. The designer creates a datapath structure and then places it in a bit-sliced style, as shown in Figure 2. Cells that are operating on one bit are placed in horizontal rows, and each row is repeated and abutted vertically for each bit. It is the designer’s responsibility to ensure that the regularity of the structure is preserved in all the physical design stages. This is not a trivial task.
Figure 2: Datapath structure placed in a bit-sliced style
Benefits of custom datapath design
Custom datapath structures, though non-trivial to create, help implement greatly optimized structures. The biggest benefits are better performance, lower power and smaller area. By maintaining the regularity of cells, designers are able to achieve multi-gigahertz clock frequency, reduce clock skew and power. For high-speed designs, reducing parasitic (RC) delays and skew is extremely critical. Placing cells closer reduces area and wire length, and mitigates routing congestion. Aligning cells and pins creates straighter wires and reduces vias and jogs. At advanced process nodes, this helps reduce cost and improve manufacturability. Custom datapath structures once created are quite frequently used as intellectual property (IP), with predictable results.
Good article, datapath and compiled layout makes a lot of sense. In fact an entire company was formed around this very concept called Silicon Compilers in the 1980s, then acquired by Mentor in the early 1990s. There were two compiler tools: Genesil and GDT. Earlier while at Intel I wrote my own layout compilers to produce parts of a Graphics Chip automatically.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.