Part 1 of this series discussed timing as part of functional safety, and uses the example of a seat memory system for analysis of faults.
This part analyzes the seat memory system when a switch fails and how the software must respond in detecting the failure and stopping any motion. Modeling timing and "critical event" chains are introduced to determine predictable reactions in real time.
Mechanical design, electronics, and software will have a common architectural blueprint to derive critical event chains and timing budgets. The earlier (by using model based methods) this can be tested, the faster a robust architecture can be found and the safety goals achieved. The example demonstrates that even small functions aren't trivial especially when they rely on complex integrated systems. Nevertheless it is shown that the modeling of timing and performance is feasible with the right methods and tools.
For the complete second article, including integrating safety and non-safety functions into an ECU, click here, courtesy of Automotive Designline Europe.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.