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Two methodologies for ASIC conversion

5/31/2011 06:30 PM EDT
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juszza
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re: Two methodologies for ASIC conversion
juszza   6/10/2011 12:25:23 AM
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This is a great article. What it demonstrates is that FPGA-to-ASIC conversion is still a clunky hack. What is really needed is a single platform that is both reprogrammable during the design and test phase, low NRE for release-to-production and has all the density, power and cost benefits of an ASIC for volume production.

GalGilat
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re: Two methodologies for ASIC conversion
GalGilat   6/5/2011 3:36:19 PM
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Hi, That is a very nice article. 2 comments: 1. Beyond the flow, there is a difference in the unit price: while eASIC is based on structured ASIC, the die size and the process are fixed. On the other hand KaiSemi which targets the solution to standard-cell of standard fab processes as a custom ASIC, fits the optimized die size and process lib which bring a major cost reduction. 2. "The oppurtunity to enhance the design during conversion" is a real functional risk for a one-time ASIC burning. KaiSemi could support it, but it rather provide a functional gurantee over a final working FPGA.

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