One of the most important aspects of this mission is to gain an understanding of the performance of the Virtex-4 device in a LEO environment. While Xilinx has hardened this FPGA for spaceflight, SEUs will still occur and affect both the configuration data and the FPGA registers, RAM and digital clock managers (DCMs). This mission therefore configures the FPGA to use most of the internal logic, RAM and DCMs. We then monitor the performance of this device using another one-time programmable hardened device, which passes performance statistics back down to the ground for analysis. Interestingly, on this mission we are less concerned with SEU- and radiation-mitigation design techniques than on ensuring that these events can be captured such that they can be detected by a monitoring FPGA, allowing for the generation of real in-flight performance statistics.
This aspect of the design presented some interesting engineering challenges. For example, an SEU could affect signals such as the DCM locked signal and incorrectly indicate that the DCM has been affected by an SEU, when in reality it has not. To counter this potential problem, the FPGA design engineers came up with a method of using counters to monitor the DCMs and make sure they are locked to the correct frequency. Should the counter freeze or increment at a different frequency, it is indicated by comparing it with the other counters, allowing for an FPGA reconfiguration if required.
U.K. Space Agency will launch UKube1 in January 2012. The CubeSat will provide data on both of our experiments for at least the mission lifetime of one year. This mission will demonstrate the suitability of high-performance FPGAs for use in LEO missions and microsatellite architectures as well as hopefully allowing the use of high-performance FPGAs in other missions of longer duration.
The UKube1 is expected to be just the first of a national CubeSat program in the U.K. The architecture developed for UKube1 lends itself to adaptation for use on future missions to gain further understanding of, and experience in, using large, high-performance FPGAs in orbit. Potential adaptations for the next mission would include a demonstration of in-orbit partial reconfiguration and in-orbit readback and verification of the device configuration. Unfortunately, due to the time scales involved in the development of UKube1, these experiments could not be incorporated on this maiden voyage.
The UKube1 architecture using the Xilinx Virtex-4 family of devices also lends itself to evolution into a system-on-chip-based controller that could serve as a micro- or nanosatellite mission controller.
Comparing FMCs with PMCs/XMCs for harsh environments
Using FPGAs in mission-critical systems
Understanding and mitigating tin whiskers
Xilinx FPGAs beam up next-gen radio astronomy
Xilinx rad-hard FPGA reaches for the stars
When perfect is good enough
Single event effects (SEEs) in FPGAs ASICs and processors
Transfer from FPGAs for prototype to ASICs for production
Design security yields secure FPGAs for mil/aero applications
About the author:
Adam Taylor is Principal Engineer at EADS Astrium.