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3-D IC design: New possibilities for the wireless market

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re: 3-D IC design: New possibilities for the wireless market
docdivakar   6/13/2011 10:20:10 PM
@Samta Bansal & the gang: thank you for a summary. You have posed a question in one of the early paragraphs of the article -whether design teams (outside of a handful of large semiconductor companies) will have the EDA tools... how ever, there is scant coverage of this in your article (albeit a summary at the end). While I agree there are no major showstoppers, what is needed to supplement the existing EDA tools are methodologies that validate stacked physical design after a 3D pathfinding has been completed as well as multidisciplinary / multiobjective approaches to optimize overall 3D floor planning. Since you also brought up IP blocks, herein lies one of the quandaries for the 3D flow (as you also have mentioned): it is not all BEOL- or FEOL-desin approach when 3D is involved. It is product/stack-dependent. By the way, there is an error in units above: ...finding a method to probe TSVs with a diameter of 10 mm each and on a 50-mm grid... I assume you are referring to 10um not mm (which is as wide as Lincoln Tunnel in the Semi world). For those of us who spent some time in the wafer probing business, some approaches become rather obvious for situation like this: variants of membrane probes with microbumps, or, alternately MEMS probes with well-designed contact spring-like tips. MP Divakar

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