The phase-locked loop (PLL) is one of the key building blocks in many communication systems; providing a means for maintaining timing integrity and clock synchronization. The PLL can be used in various applications such as timing extraction from data streams, jitter mitigation and frequency synthesis.1,4,7
In this article, we describe the fundamental properties of a charge-pump PLL (CP-PLL). The CP-PLL derives its name from the fact that the phase detector (PD) output is a current source as opposed to a voltage source and "pumps" current into and out of the loop-filter. This form of PLL is popular because it is adaptable to integration in microcircuit devices. Therefore we focus the discussion on methods suitable for ASIC design. We provide mathematical models to study key parameters affecting the loop-bandwidth, peaking, jitter, noise and transient response.
The basic PLL (Fig. 2-1) consists of four fundamental components:
* Phase detector, PD
* Loop-filter, z(s)
* Voltage Controlled Oscillator, VCO
* Divider, (1/n)
The phase detector (PD) compares the input signal fi with a reference, or feedback signal fr, to produce an error signal error signal Ĝe that is proportional to the phase difference between fi and fr.
The loop-filter extracts the low frequency content Ĝz of the phase error signal Ĝe, which is fed to a voltage-controlled oscillator (VCO). The VCO produces an output frequency v proportional to the low frequency error signal Ĝz. The output signal v is typically divided by a 1/n counter producing the reference signal r.
The reference signal fr is fed back to the phase detector, forming a closed-loop system. Using negative feedback, the loop ensures that the input frequency fi equals the reference frequency r and also that the phase of i and r are fixed with respect to each other. However, the absolute phase difference between i and r need not be zero. Note the divider inside the loop serves as a frequency multiplier. The output may be taken from either v or r therefore the output frequency is given by
A modification to the basic PLL is obtained by inserting an additional divide by m counter outside the loop (Fig 2-2).
Unlike the n divider inside the loop, the m divider outside the loop acts as a frequency divider. By adjusting n and m you can obtain a fractional rate frequency multiplier suitable for frequency synthesis. The output frequency is given by.
The charge-pump PLL (CP-PLL) is an extension of the basic PLL requiring the addition of a charge-pump between the phase detector and loop-filter. A specific embodiment (Fig 2-3) uses a three-state phase detector (3PD) which is used for the analysis going forward. Each of the blocks is discussed in the following sections.
3. PLL Components
3.1. Voltage Controlled Oscillator
One implementation of the VCO (Fig. 3.1) suitable for ASIC design consists of a series connected Voltage to Current Converter (V2CC) and a Current Controlled Oscillator (CCO).
The V2CC takes the control voltage vc and converts it to a proportional bias current ibias. The bias current is fed to the CCO which generates an output frequency proportional to the bias current.
A representative implementation of a V2CC is shown in Fig. 3-2. The operational amplifier adjusts the gate voltage of Q1 such that the current flowing through Q1 is
The current mirror consisting of Q2 and Q3 develops the Pbias and Nbias voltages respectively. These bias voltages are used to set the bias current in the CCO.
The VCO and CCO gains are defined respectively as
The CCO may be implemented as a simple ring oscillator (Fig. 3-3). The ring oscillator consists of n series-connected delay cells with the output of the last cell fed back to the input of the first.5,6
According to the Barkhausen criteria10 the ring will oscillate if: (1) the total magnitude of the gain around the loop is unity and (2) the total phase shift is zero or an integer multiple of 2pi radians at the oscillation frequency. In practical applications, the total loop gain should be slightly larger than unity to ensure positive feedback is maintained in the presence of device variations.
When the gain is larger than unity, the oscillation amplitude will be limited by the onset of device nonlinearity. In the case of the inverter, the nonlinearity acts as a hard limiter. It is clear that the total gain for n inverters is greater than unity.
Each stage provides pi/n phase shift and so it requires two passes through the ring to acquire the necessary 2pi radian phase shift. Therefore, the frequency of oscillation is6
In order to establish a variable delay element responsive to the VCO control voltage, the delay for each cell can be made to depend on the amount of current used to bias the cells. One method known as a Current-Starved Inverter is shown in Fig 3.55.
The NBIAS and PBIAS voltages generated from the V2CC block, establishes the cell bias current for the N and P devices respectively. The cell delay is determined by the bias current IBIAS, the output capacitance Cx and the Schmidt trigger thresholds vth
An alternative version of a current-starved inverter operating directly from the control voltage vc, is shown in Fig. 3-75 The control voltage sets the reference current for Q1 and Q2 The bias currents for Q4 and 3 are mirrored from Q1 and Q2 respectively. The bias current in Q3 and Q4 may be scaled up or down with respect to the reference current in Q1 and Q2.
If the propagation delay of the Schmidt trigger is much less than the delay Td, then the cell delay is approximately6.
From which the oscillator frequency is
Equations (3.7) and (3.8) indicate that when the bias current is increased the delay decreases and the oscillator frequency increases. When the bias current is decreased the delay increases and the oscillator frequency decreases.
The output of the loop-filter Ĝz(t) is the control voltage vc for the VCO. The VCO clock frequency v is proportional to the control signal therefore
The proportionality constant kv is the VCO gain constant (radians/volt-sec).
Since frequency is the time-rate-of-change of phase, then the output phase of the VCO is proportional to the integral of frequency, thus
The charge-pump (Fig 3-8) consists of a set of current sources with magnitudes of IP1 and IP2 amps respectively. In most cases the current sources are symmetrical thus IP1 = IP2 = IP.
One source is connected to the positive supply rail while the other is connected to the negative supply rail. The sources are separated by two switches S1 and S2. The output of the phase detector provides the gating signals U (up) and D (down) which turn on S1 and S2 respectively. The phase detector is designed such that switches are never on simultaneously.When U is high and D is low then S1 is on and S2 is off which causes current to flow out of the pump and into the loop-filter. When U is low and D is high then Q1 is off and Q2 is on which causes current to flow out of loop-filter and into the pump.
A representative CMOS charge-pump circuit is shown in Fig. 3-9 and is similar to the output stage of the current starved inverter (Fig 3-5). The VPBIAS and VNBIAS voltages set the positive and negative charge-pump currents respectively.3,5
The loop-filter is typically a simple passive filter (Fig. 3-10). The purpose of the loop-filter is to average the phase-error signal from the 3PD.
The significance of the loop-filter regarding loop-stability and steady-state tracking error is discussed in section 4.2.
3.4. Three-State Phase Detector
The 3-state phase detector (3PD) is a finite state machine with three defined states labeled S1, S2 and S3. The rising edges of the R and V inputs denoted by R and V respectively cause the 3PD to transition from one state to another based on the following state diagram (Fig. 3-11).
Note that U and D are never in the "on" or "1"state simultaneously.
The pulse width t is proportional to the relative phase difference between R and V. If the phase of R leads V (Figure 3-12) then the pulses will appear on the U output and the sign of t is positive. If the phase of R lags V then the pulses appear on the D ouput and the sign is negative (Fig. 3-13).
The U signal causes pump current to be positive for a duration of t seconds and the D signal causes positive pump to be negative for a duration of t seconds. Therefore we can express the output of the phase detector and charge-pump as a single variable
A simple implementation of a 3-state phase detector and charge-pump is shown in Fig. 3-15. The phase detector consists of a pair of D-Flip Flops and an AND gate. The summing node subtracts the D signal from the U signal providing the polarity for t and the multiplier modulates the pump current Ip with t to generate the pump current ip.
As discussed previously, the 3PD generates an error signal Ĝe proportional to the phase difference between the input and reference clocks.
The proportionality constant kd is the phase detector constant. In the case of a charge-pump PD the units are amps/radian (if the PD is a voltage source the units are volts/radian).
The phase detector gain including the charge-pump is determined as follows: The on-time for either U or D is
From which the phase detector constant (amp/rad) is3
The phase detector average output current iavg as a function of phase error Ĝe, is shown in Fig 3-16. The slope between -2pi and 2pi is linear and corresponds to the phase detector gain kd given by (3.19). For 0 < Ĝe < 2pi, the arrow indicates that the VCO will tend to drive the phase error towards zero by increasing the VCO frequency (down hill). For -2pi < Ĝe < 0, the arrow indicates that the VCO will tend to drive the phase error towards zero by decreasing the VCO frequency (up hill).
In addition to functioning as a phase detector, the 3PD also operates as a frequency detector; a characteristic not shared by some other types of phase detectors (e.g., XOR type). This feature is useful since it aids in frequency acquisition and also prevents the loop from locking to higher order harmonics of the input clock. To illustrate the frequency detecting ability we consider two cases.
If the R frequency is higher than the V frequency, the rising edges of R will appear to walk to the left with respect to V (Fig. 3-17), forcing the 3PD to toggle between states S2 and S3. This causes pulses to appear on the U output of the PD. The resulting average pump current is positive (into the loop-filter) resulting in an increase in the VCO frequency.
Case 2: R < V
If the R frequency is lower than the V frequency, the rising edges of R will appear to walk to the right with respect to V (Fig.3-18), forcing the 3PD to toggle between states S1 and S2. This causes pulses to appear on the D output of the PD. The resulting average pump current is negative (out of the loop-filter) resulting in a decrease in the VCO frequency.
About the Author
Mr. Pattavina has worked for 30 years in the data and voice communications industry, specializing in: broadband access, high-reliability IP streaming, and TDM carrier-class communication systems. Mr. Pattavina holds a Master of Science degree in electrical engineering from Northeastern University. He has authored four patents and seven technical publications in electronics, reliability, and communication systems.