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Product How-To: Controlling Power in Cypress Programmable SoC (PSoC) devices

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Sridhar_S_R
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re: Product How-To: Controlling Power in Cypress Programmable SoC (PSoC) devices
Sridhar_S_R   7/22/2011 3:25:52 AM
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Tools today support "power aware" simulations. The following link gives a good introduction http://www.mentor.com/products/fv/questa-power-aware-simulator. Simulators create a virtual power network based on UPF description. This interacts with the RTL that is supplied to the simulator. As an example, if power_down_n (in Fig 5) is asserted in RTL during simulations, all signals in power domain VCC_0 are corrupted by the simualtor.

DrFPGA
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re: Product How-To: Controlling Power in Cypress Programmable SoC (PSoC) devices
DrFPGA   7/21/2011 4:39:32 PM
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It would be interesting to learn more about the simulation process for these types of designs. How is it different from standard digital logic simulation?

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