This paper presents PSoC design aspects that enable users of PSoC devices from Cypress to implement low power systems. It explains PSoC power modes and maps the power modes to design elements. It touches upon the UPF (Unified Power Format) that enables designers to concisely capture the system power architecture. The main focus of this paper is on low power concepts that relate to shutting down power to blocks in a chip. These general techniques are applicable to any SoC (System on Chip) and not necessarily to a PSoC.
As shown in Figure 1, PSoCs are mixed-signal chips that combine programmable analog fabric with programmable digital fabric along with a with a collection of of analog and digital IP (Intellectual Property) blocks. With the range of IPs available on a PSoC, users can realize extremely complex functionality using a single chip, which otherwise would require a large number of discrete components.
This paper does not delve into the power savings associated with the analog circuits in the PSoC. For digital CMOS circuits, there are 3 major components of power dissipation: (i) Dynamic, (ii) Static, and (iii) Direct path short-circuit . Vast amount of literature are available on saving power in each of these areas. Not surprisingly, shutting down the power to a functional block has the maximum impact on power savings. It affects all three components mentioned above as well as eliminating power dissipation by analog blocks. With the advent of the Unified Power Format (UPF), the power architecture of an SOC can be captured in a single file without modifying the RTL (Register Transfer Level) description.
Figure 1. PSoC block diagram
The paper is organized such that it first describes the power modes used in PSoCs that provide control over the power consumption of the device. It later relates these power modes to the design elements that make the power modes possible. Finally, it provides an introduction to UPF along with an example that makes realization of low power systems easier.
A power mode specifies a combination of power consumption, wake up time, and wake up sources of a chip. Power modes supported in PSoCs include Active, Alternate active (or Standby), Sleep, and Hibernate in decreasing order of power consumption . PSoC devices are accompanied by API (Application Programming Interface) that can be used to enter into any of the modes. Current consumption and wakeup time for these modes are provided in Figure 2. These numbers are typical values and may change significantly based on user application, system activity, and device configuration.
Figure 2. PSoC power modes, currents, and wakeup times
In the Active mode, the processor can selectively enable or disable blocks. All blocks can be functional in this mode and typically would dissipate most power. Power savings still do happen in this mode, but these are to the extent of disabling clocks to blocks not being used. That is the reason why wake up times are negligible.
A mode in which the entire system can be shut-off (except for a wake-up controller) is the Hibernate mode. In this mode the processor is placed into an idle state and the rest of the peripherals also are inactive. Only the Hibernate regulator is kept alive in order to retain any critical states of the system that will be required on power-up. Modes other than Active and Hibernate can be defined based on the expected activity of the processor and peripherals.
Power modes are controlled by firmware for maximum flexibility. When a “WFI” instruction is executed, it conveys the processor to get into a Sleep mode and wait for an interrupt. Typically, when the processor is instructed to enter the Sleep mode by the firmware, the processor asserts a “SLEEPING” signal to indicate to the global power controller in the SoC that the processor can be disabled. This, along with special memory mapped registers, can be used to get into either of the power modes.
Associating power modes to low power design elements
Implementing the power modes described in the previous section requires special cells. These are summarized in Figure 3 and their functions are as follows:
Isolation cells: In normal operation mode when blocks are not powered down, isolation cells simply pass logic values. When a block is powered down, isolation cells ensure that outputs are clamped to a known logic value. The logic value can be ‘0’, ‘1’ or most recent state
State Retention Power Gate (SRPG): SRPG are cells that keep a copy of register contents in a shadow register when SAVE is asserted. When register is powered up and we intend to retrieve its value, RESTORE has to be asserted. This copies contents of the shadow register back to main register.
Power switch: These are cells that turn ON/OFF the supply. Great care must be taken in sizing these switches to avoid excess “IR” drop. Switches can either be in each of the standard cells (fine) or multiple cells can be driven with a single power switch (coarse).
Level shifters: These are cells that must be inserted on a signal when the signal is communicated across blocks operated with different supply rails. For good reasons, 2 different types of levels shifters exist for a low to high or high to low voltage level shifting.
Figure 3. Basic components for power control
A power manager translates power mode requirements to signals as illustrated in Figure 4. Note that signals with an “_N” suffix are active low.
Figure 4. Timing of power control signals
In order to power down for Hibernate mode, hardware must generate signals with the following timing sequence:
A block that is intended to be powered down must be isolated first so that neighboring blocks still receive valid digital signals
A SAVE signal must be asserted so that SRPGs are placed in retention mode
At this point all sequential and combinational cells are in a state to accept a power down. The POWER_DOWN signal must be asserted.
By comparison, the power-up timing sequence has to be as follows:
De-assert the POWER_DOWN signal
De-assert reset to have an effect of power-on reset
SRPGs copy contents of their shadow register to their main register when RESTORE is asserted
Allow isolation cells to pass normal values.
Note that RETAIN_N can be used instead of SAVE and RESTORE signals.
The Unified Power Format (UPF)
The task of implementing the design elements described in previous section is simplified by means of the UPF methodology. A UPF file allows the specification of power supply distribution by means of a collection of commands. Details of the commands provided by UPF are available in . A single file can be created for a particular SoC that captures the entire power intent. A UPF file thus created is taken along with the design file and used by both simulation and synthesis tools. Figure 5 provides one such example.
Figure 5. Example UPF file
As can be observed from the commands used in Figure 5, specifying a power supply architecture is greatly simplified by using the UPF. Commands in this example can be related to elements depicted in Figure 3. A power state table (PST) is part of the example. The PST captures legal voltage level combinations of all power domains. This information is used by simulation and synthesis tools, due to which any errors in the power supply architecture are flagged very early in the SoC development process.
PSoCs are emerging as a powerful solution due to their ease of use and ability to replace large number discrete analog and digital components. Simply replacing a large number of discrete components provides a significant power advantage. As the icing on the cake, the PSoC itself is designed to guarantee ultra low power consumption. This paper has provided a brief overview as to how this is made possible. Power modes are provided by the PSoC that are implemented as complex low power structures that almost eliminate any chance of wasted power. The intent of accomplishing low power consumption is simplified further by the usage of the UPF.
I would like to thank Anand Moghe and Deepak N K for their feedback on this paper.
 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL 27, NO 4. APRIL 1992. Low-Power CMOS Digital Design Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen.
 “Accellera” Unified Power Format (UPF) standard, Version 1.0: http://www.unifiedpowerformat.com/imagses/UPF.v1.0_Standard.pdf
 Michael Keating et al. “Low Power Methodology Manual For System-On-Chip design”
 Palani Subbiah, “Achieving Flexible Power Management for
 Embedded Systems” http://www.cypress.com/?docID=20019
 Kantesh Kudapali, “Using sleep and hibernate modes in PSoC®3” AN66083 : http://www.cypress.com/?docID=26820
 “Creating Low-Power Digital Integrated Circuits - The Implementation Phase” Cadence white-paper : http://www.cadence.com/rl/Resources/white_papers/Power_Aware_implementation_WP.pdf
About the author
S R Sridhar is a senior electronic design engineer at Cypress Semiconductor. He has worked on the FPGA prototyping of Cypress's fourth-generation touchscreen controller. Prior to this, he architected and developed RTL IPs for H.264 high definition video codecs at Ittiam systems Pvt. Ltd.
After getting his Bachelors in Electronics in 1999 from B.V.B Hubli, he worked for three years in custom circuit design and layout at Karmic Design Centre, Manipal, India.
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