Signal integrity will matter more in next-generation flash devices, and several changes in the technology will make managing signal integrity more critical. For example, data rates in these devices will range from 400 MHz to 6 GHz. To support the faster data rates, edge rates will have to become 10 to 100 times faster. Demand for increased storage capacity will also drive the need for denser packaging and more complex interconnects.
Pressure to reduce costs will force you to make trade-offs that affect signal integrity, such as using lower-cost materials or even eliminating the use of ground planes. As rise times become shorter, a signal’s high-frequency components become more pronounced. Higher-frequency signals are more sensitive to interconnect quality, so signal-integrity problems tend to proliferate. As signal frequencies increase, signal loss also increases. Therefore, high-frequency components of fast-rise-time signals experience more loss than the low-frequency components, leading to signal distortion and ISI (intersymbol interference).
Understanding the causes of signal-integrity problems and their remedies is critical. Signal-integrity problems include reflections and distortions, crosstalk, ground bounce, and jitter. Reflections and distortions relate to signal quality on an individual net. When a signal encounters an impedance discontinuity, it generates a reflection that becomes further distorted as it continues along the net. The reflection travels from the impedance discontinuity in two directions—toward the receiver and back to the driver. The reflections themselves react to other discontinuities, creating further reflections that distort the true signal in complex ways, generating effects such as ringing, overshoot, and slope reversal. Careful design to maintain well-controlled impedance along key traces is the best way to improve signal integrity.
Managing signal integrity in tomorrow’s high-speed flash-memory-system designs figure 1Crosstalk-induced signal-integrity problems involve multiple signal nets. If you place an active net near a quiet one, capacitive and inductive coupling can cause some of the energy from the signal on the active net to couple over to the quiet side (Figure 1).
The quality of grounding and current-return paths in your design is among the biggest factors affecting crosstalk. In most PCB (printed-circuit-board) designs, ground planes are available as return paths. This approach is best if you can afford the extra plane. If cost pressure forces you to eliminate using a ground plane, you must use other strategies, such as placing a ground trace next to the signal or using differential instead of single-ended signaling.
Ground bounce also affects signal integrity and relates to power distribution. As with any network that has interconnects, inductance exists in power and ground networks. As the I/O signals transition from zero to one or one to zero, transient current flows in the power-distribution network. Many signals’ switching at once generates large transient currents. Any inductance or resistance in the power- and ground-distribution network converts these transient currents into voltage spikes that appear as noise in other signals or even as a shift in the ground voltage. Ground planes or multiple ground or power connections reduce the impedance and therefore the SSO (simultaneous-switching-output) noise. Using lower voltage swings and protocols that minimize the number of signal transitions also helps.
Managing signal integrity in tomorrow’s high-speed flash-memory-system designs figure 2Jitter issues also affect signal integrity. Reflections, crosstalk, and SSO all can contribute to jitter. In addition, ISI created on lossy channels, PLL (phase-locked-loop) noise, EMI (electromagnetic interference), differences in transmitting and receiving threshold voltages, and ordinary delay mismatches in internal logic can generate jitter. The strategy for managing jitter differs, depending on the cause of the jitter. Proper shielding can help with EMI-induced jitter, but it cannot fix a noisy power supply. Knowing whether the jitter is random, periodic, or correlated to some other event in the system helps you determine the best ways to address the problem (Figure 2).