Calculating power loss in a switching MOSFET is not as straightforward as it first seems. Many factors come into play. How do the loss characteristics of trench (or vertical) and lateral MOSFETs differ? How does the relative impact of conduction and switching loss change in applications at low to moderate power levels? And how do the unique characteristics of each MOSFET’s structure impact the development of a high efficiency design?
Major causes of power loss
Power loss in a MOSFET comes from two sources. Every MOSFET has a resistive element, so it dissipates power as current is conducted through the device. The resistive parameter is described as on-resistance, or RDS(ON). These conduction losses are inversely proportional to the size of the MOSFET; the larger the switching transistor, the lower its RDS(ON) and, therefore, its conduction loss.
The other source of power loss is through switching losses. As the MOSFET switches on and off, its intrinsic parasitic capacitance stores and then dissipates energy during each switching transition. The losses are proportional to the switching frequency and the values of the parasitic capacitances. As the physical size of the MOSFET increases, its capacitance also increases; so, increasing MOSFET size also increases switching loss.
These sources of power loss create a significant challenge for power supply designers. While a larger MOSFET will exhibit less on-resistance – and consequently lower conduction loss – its larger area drives up parasitic capacitance and switching loss. In many cases, moving to a larger MOSFET to reduce conduction loss will result in so much increased switching loss that it outweighs the conduction loss savings. Designers typically try to achieve a balance between conductive and switching losses for a particular application.
Many manufacturers of discrete switching MOSFETs employ a vertical trench process where the source of the MOSFET is located on the top of the silicon, the drain at the bottom, and current flows vertically through the device (incidentally, that is why the copper tab on a power package is typically at drain potential).
Trench MOSFETs typically exhibit relatively low on-resistance, but high parasitic capacitances between the gate, drain, and source. Other MOSFETs in the market follow a different approach, employing a lateral MOSFET architecture that places the source and the drain on top of the silicon, with current flowing horizontally across the structure. These lower-density MOSFETs combine moderate levels of on-resistance with relatively low parasitic capacitances.
In MOSFETs using either a trench or lateral architecture, there is a distinct relationship between on-resistance and capacitance. But it is important to remember that the ratio of RDS(ON) per unit area compared to capacitance per unit area is different for each, and each approach offers distinct advantages.
Since trench MOSFETs exhibit relatively low RDS(ON), designers can compensate for increased switching losses by using a larger transistor. At the same time, switching losses for a given on-resistance in a MOSFET using a lateral architecture can be less than half of those exhibited by a comparable trench MOSFET, allowing them to offset the higher conduction loss that their higher on-resistance generates.
Figure 1. Simplified AC capacitance model of a primary switch
Two factors contribute to switching loss: turn-on loss (see Figure 1), or the energy used to charge drain-source capacitance (also referred to as output capacitance, Coss); and crossover loss, or the energy lost during turn-on and turn-off transitions. Both of these factors play an increasingly important role in applications at lower power levels.
Power loss due to RDS(ON) is proportional to primary peak current. Discrete solutions using a trench process attempt to balance their relatively high switching losses with lower conductive losses. But at lower power levels, the maximum switching frequency is limited for designs following this approach.
Drain source capacitance (Coss) is present in all MOSFETs. In each cycle, the energy stored in Coss is dissipated in the MOSFET, but the amount of energy dissipated can vary widely depending upon the MOSFET’s structure. Lateral MOSFETs exhibit Coss that is significantly lower than that found in trench devices.
Table 1 offers an excellent example. Product A is a switching MOSFET that uses a proprietary lateral structure. Products B through E are trench MOSFETs from various leading manufacturers. Product A exhibits an RDS(ON) specification that is 2.5× to 4× higher than its competitors. Yet if we look at the output capacitance (Coss) of the MOSFET in pF at an input voltage of 400 VDC, we see it offers significantly lower power loss (assuming parasitic winding capacitance (Cp) = 20 pF and switching frequency (f) = 65 kHz).
Table 1. Switching power loss for different MOSFET structures
A trench MOSFET achieves low RDS(ON) at the expense of a large interface area between the gate, drain, and source, which results in larger parasitic capacitance. In contrast, a lateral MOSFET features a lower density structure which conducts current across the surface of the silicon. This structure has smaller interface areas between gate, drain, and source, resulting in significantly lower overall parasitic capacitances.
Energy lost during drain-current and drain-source voltage transitions during turn-off, or crossover loss, also contributes to overall switching loss. If we examine the turn-off of a hard-switched topology during the transition, current does not instantly fall to zero, the channel is still in conduction, and an increasing voltage is developed applied across the drain-source channel of the MOSFET, resulting in crossover loss.
Crossover loss is a function of the switching speed of the MOSFET (gate resistance, gate source capacitance, and gate drain capacitance). For a given gate drive, lateral MOSFETs achieve faster transition which results in lower crossover loss as compared with a trench MOSFET.
Lower crossover loss contributes to lower losses in a number of ways. For example, MOSFETs using a lateral structure require significantly less gate charge to turn on. As Table 2 illustrates, Product A is fully turned on (the conduction channel is fully enhanced) at 6 V (VGS = 6 V), while comparable trench devices require 10 V.
Table 2. Charge characteristics due to parasitic MOSFET capacitance
The ability to fully turn on at a lower gate voltage results in lower losses in the gate driver and has an impact on turn-on times for the transistor. For instance, gate source capacitance (QGS) normalized to a MOSFET sized to provide 1 ? RDS(ON) is 1.3 nC for Product A. QGS for comparable trench products ranges from 4.02 nC to 6 nC. Similar large differences exist for gate-to-drain Miller charge (QGD) and overall gate charge (QG).
As application power levels drop, the discrepancy in switching loss becomes increasingly significant. For example, at 500 W, conduction loss represents the major source of total MOSFET power loss. Moreover, around these power levels, designers typically opt for soft-switched ZVS topologies that greatly reduce switching losses. However, for applications in the 50 W to 75 W range, conduction loss and switching loss contribute similar amounts of loss. In applications at about 25 W and below, switching loss begins to dominate loss calculations.
This key distinction can have a significant impact on an engineer’s calculation of the most efficient power solution for low-to-mid-power solutions. Table 3 depicts the power loss budget in a typical 35 W adapter using either a discrete trench MOSFET and controller or a TOPSwitchä high-voltage lateral MOSFET manufactured by Power Integrations which integrates a driver, PWM controller, and protection functions.
Table 3. Estimated power loss in a 35 W adapter
At first glance, the discrete solution seems to offer a more efficient solution. RDS(ON) for the lateral MOSFET is almost three times higher than RDS(ON) for the discrete solution. Upon closer examination, however, it becomes apparent that the lateral MOSFET offers significantly less switching loss due to lower crossover and turn-on losses. Overall, the TOPSwitch-based solution offers a 13% reduction in power loss relative to the discrete trench MOSFET solution.
Perhaps more importantly, these advantages in terms of lower switching loss offer power supply engineers increased design flexibility. Typically, designers using trench MOSFETs compensate for higher switching loss by switching at a lower frequency. In Table 3, for example, the discrete trench-MOSFET-based solution operates at 76 kHz.
In contrast, the lateral-MOSFET-based alternative switches at 132 kHz and still delivers significantly lower switching losses. With the higher switching frequency, on-time per cycle is lower, allowing designers to use a much smaller cored transformer while maintaining the same flux density.
This advantage allows power supply designers to build a comparably efficient solution operating at twice the switching frequency while occupying significantly less space and reduced transformer cost. The lower switching losses translate directly into a smaller, more cost-efficient solution.
The common assumption that many engineers make that power loss in a MOSFET is a direct function of RDS(ON) has some validity. In higher-power applications, conduction loss is typically the primary cause of energy loss in switching MOSFETs.
But for a wide variety of applications in the low-to-mid-power range, this assumption is too simplistic. To calculate true power loss in the growing array of applications in the low-to-mid-power range, engineers must carefully consider the impact of switching losses in these applications, and the fundamentally different performance capabilities inherent in trench and lateral MOSFETs.
About the Author
Andrew Smith is the Engineering Training Manager at Power Integrations, where he is responsible for developing and delivering in-depth technical training on all power applications involving PI products. Prior to joining PI, Andrew spent 11 years as a power supply design engineer before transitioning to a sales and marketing role at Advance Power, then Vishay Siliconix. He holds a Bachelor of Engineering, Honors Degree (First Class) in Electrical and Electronic Engineering from Middlesex University in England.
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