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PCM Progress Report No 5: SSDs, MLC, and scaling

8/7/2011 01:12 PM EDT
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rbtbob
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
rbtbob   8/15/2011 9:03:08 PM
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One of your contacts and I have been discussing abandoning the silicon substrate and using CVD or AVD to build the PCM on an alternate substrate. My suggestion is that the materials folks design a chalcogenide substrate to meet the necessary specs. If that were done, couldn't one of the specs for the chalcogenide substrate be that it allow for a laser driven modification of the state of the cells AFTER fabrication? Getting even farther out in la-la land, the production could be changed to a continuous ribbon of chips just one chip wide. Now you can have the moderator boot both me and Volatile off the comments area so you can get serious with the real engineers and researchers :-) Should that be done, I may as well go out expressing my unsupportable opinion that the optimum chalcogenide for the PCM memory material includes arsenic and is doped with terbium.

R G.Neale
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
R G.Neale   8/15/2011 7:57:09 PM
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A number of people have contacted me with respect to the energy aware paper. If MLC PCM are going to be part of the solution to PCM scaling problems, then how do we decide which of the levels 00,01,10 or 11 in a four level cell are the best for energy awareness. The problem is further complicated because a number of the MLC techniques require an initial reset pulse before the write/ease steps to the get to the target level are started. Even if that is not the case, set and rest pulses will be necesary to achieve the target level. The other problem I see, even for two level cells is PCM cells are manufactured in the crystallized state. That is all sectors of the memory are in the most undesirable state as far as energy awareness is concerned. If I initially write to a few sectors, these will also be the best sectors as far as energy awareness is concerned and might get written to destruction.

Volatile Memory
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
Volatile Memory   8/15/2011 5:47:35 PM
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rbtbob: Naah, you misunderstood the "read-before-write" paper. The paper clearly shows that PCM has a higher energy consumption per bit than even DRAM, plus it does nothing to address the fundamental problem of current density, migration, and all those other issues that Mr. Neale has already covered.

rbtbob
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
rbtbob   8/15/2011 5:25:08 PM
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A paper from George Washington University makes claims of considerable improvement in PCM energy consumption. In this paper, we investigate new techniques that would perform writes to PCM with energy awareness. Our results show that we can minimize the write energy consumption by up to 8.1% by simply converting PCM native writes to read-before-write, and up to an additional 22.9% via intelligent out-of-position updates....snip Seems the researchers are going to tweak PCM into viability. http://www.seas.gwu.edu/~guruv/hotpower11.pdf

resistion
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
resistion   8/8/2011 8:47:04 AM
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The point of PCM vs flash cycle wear out was interesting. What is the flash wearout without ECC?

R G.Neale
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
R G.Neale   8/8/2011 8:28:13 AM
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rbtbob-Quotes from the cited patent “”when more than a certain amount of current passes through a phase change memory device in a reset state, its resistance and threshold voltage may change”” …..””Without being limited to theory, it may be that the reason for these disturb problems is due to the presence of crystal nuclei within the amorphous state. These crystal nuclei are the sites for the growth of the crystalline phase from the amorphous phase”” It is not a matter of “may” and “maybe”, there is no doubt that the threshold voltage changes and recovers with a time constant that exceeds the thermal time constant, however small the current and pulse width. This is initially an annealing process, the closing of dangling bonds. If and how this relates to nucleating sites is not clear. This change in threshold voltage and structure, limits read access time and is more likely than not the reason why it has so far been impossible to make stable oscillators using the “S” shaped negative resistance of a threshold switch. I think the fact that the post switching threshold recovery starts from zero as one continuous process might also teach something about the post-switching internal temperature. On nucleating sites, most structures, of necessity, use crystallized chalcogenide as one electrode structure, itself a massive nucleating site!

double-o-nothing
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
double-o-nothing   8/8/2011 2:22:32 AM
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Disturb and ease (speed) of programming are kind of conflicts of interest for any memory technology.

rbtbob
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
rbtbob   8/8/2011 1:58:29 AM
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The link below is to a new patent assigned to Ovonyx and it lists Semyon Savransky as one of the inventors: Patent 7,990,761 August 2, 2011 Immunity of phase change material to disturb in the amorphous phase http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7,990,761.PN.&OS=PN/7,990,761&RS=PN/7,990,761

Volatile Memory
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
Volatile Memory   8/7/2011 3:18:37 PM
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Mr. Neale is baaack! After falling for Mr. Savransky's and Ms. Kuzum's pseudo research (that's putting it too mildly), Mr. Neale obliterates IBM's "claims:" "How any of the material discussed above can lead anyone to be able to predict that PCM will be available for use in servers in the period 2014 to 2016 is beyond this writer." And, of course, now we have Samsung finally admitting (by buying Grandis) that PCM is a dead end. I found the Onyx system details particularly illuminating. Of course, a simple picture would have shown those huge heatsinks that make any PCM-based storage device impractical (compare to the decent NAND-based devices such as Fusion-io's). And, of course, the Onyx creators know very well that no enterprise application writes just one sector - in the real world, Onyx simply cannot compete with sparse NAND-based storage. But, hey, if anyone thinks that people will pay over $4,000 for a 10GB underperforming heater - here is the newsflash - 16GB DRAM + 16GB NAND and a battery, or a "huge capacitor" (for about $400).

resistion
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re: PCM Progress Report No 5: SSDs, MLC, and scaling
resistion   8/7/2011 2:13:25 PM
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I think below 50 nm the heat of adjacent cells cannot be neglected, and that is why 45 nm Numonyx PCM is not out yet.

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