The JEDEC standards organization has published two versions of the JESD204 high-speed serial digital interface specification for data converters and logic devices. The first revision, the JESD204 2006 specification, brought the advantages of SerDes-based high-speed serial (3.125 Gbps maximum) interfaces to data converters. The second revision, the JESD204A 2008 specification, added critically important enhancements: the support for multiple data lanes and the support for lane synchronization. Lane synchronization enables JESD204A to be used in quadrature (I/Q) sampling systems, the technology which underpins modern 3G, 3G+ and 4G broadband wireless communications. See Figure 1.
Figure 1 – JESD204 (2006) versus JESD204A (2008)
A third revision of the specification, JESD204B, has been recently completed by an international JEDEC JC-16 Task Group (Project 150.01), comprising about 65 members from 25 companies (systems OEMs and semiconductor companies). The published JESD204B specification from JEDEC is expected in 2H2011. JESD204B is expected to introduce three new enhancements that hold promise to drive this new interface into ubiquitous adoption by data acquisition system engineers worldwide. These enhancements are: a higher maximum lane rate (higher bandwidth); support for deterministic latency through the interface; and support for harmonic frame clocking (or single clock architecture data converters). See Table 1.
Table 1. JESD204 Specification Evolution
There are numerous system design merits associated with JESD204A/B as compared to legacy parallel interfaces. Briefly, these benefits include a significant decrease in the number of higher-bandwidth interconnect PCB traces, which enables increased system reliability systems (most failures occur at points of interconnect); reduced PCB complexity, which impacts both NRE costs and marginal production costs as very often the system can be implemented using fewer PCB layers; and the opening up of a critical bottleneck in the digital signal processing bandwidth of the system design, which enables higher system performance.
Higher Lane Rate to Reduce IC Package, PCB Size and Cost
The JESD204A 2008 specification defines an electrical or physical layer (PHY) that supports unidirectional, point-to-point, serial coded data rates from 312.5 Mbps to 3.125 Gbps between data converters and a logic device (FPGA, ASIC, microprocessor or DSP) separated by up 20 cm of standard FR-4 (FR402/4000-2 and FR406/4000-6) printed circuit board material. The data converters and logic devices may be connected across a backplane using one or more impedance-controlled connectors or one or more cables.
The JESD204B draft specification additionally defines the OIF Common Electrical Interface (CEI) LV-6G-SR (Short Reach) as the 6.25 Gbps PHY (from 312.5 Mbps to 6.375 Gbps), and the OIF CEI-11G-SR as the 12.5 Gbps PHY. Note that LV-6G-SR compliant transmitters and receivers are expected to achieve BER of less than 1e-15. For reference, see: http://www.oiforum.com/public/documents/OIF_CEI_02.0.pdf
Typically, TX pre-emphasis and RX equalization (EQ) on the converters and FPGAs/ASICs is an option at 12.5 Gbps, depending on the length of the transmission line. JESD204B retains the 20 cm “reach” (length) plus one or more impedance-controlled (100 ohm differential) connectors transmission line characteristics as JESD204A. High quality PCB material such FR-4 Nelco 4000-13SI is also potentially necessary at 12.5 Gbps, again depending on the reach of the transmission line (transmission lines are called data “lanes” in JESD204A/B). Lanes less than 20 cm in length may not require TX pre-emphasis and RX EQ. (Altera Corporation has information on its website relating to TX pre-emphasis and RX EQ.)
Like JESD204A, 8B/10B is the coding scheme for JESD204B. Generally speaking, more efficient coders, such as 64B/65B, are used at higher line frequencies; however, it was considered “out of scope” to redefine the coding scheme for JESD204B by the JEDEC 150.01 Task Group. If there is sufficient industry interest, the coding scheme could be redefined as part of a future JESD204C revision.
The JESD204B specification includes new channel models for the 12.5 Gbps PHY, specified as frequency-dependent Insertion Loss Deviation (ILD) masks required for 20 cm FR-4 (FR402/4000-2 and FR406/4000-6) and one or more impedance-controlled connectors or cables. Note that JESD204A specifies insertion loss more simply: the total insertion loss shall not exceed 6 dB from DC to 0.75 times the utilized baud rate.
JESD204A specifies TX and RX return loss (both single-ended and differential) with a single number: 7.5 dB minimum for TX; and 10 dB minimum for RX. In the JESD204B spec, the transmitter differential output return loss minimum (from 100 MHz to 0.75 times the utilized baud rate) is 8 dB, and the common mode return loss minimum (from 100 MHz to 0.75 times the utilized baud rate) is 6 dB. The receiver return loss minimums are the same.
JESD204A defines total jitter (TJ) as the sum of deterministic jitter (DJ) plus random jitter (RJ), measured in peak-to-peak normalized bit times or “unit intervals”. In JESD204A with the 3.125 Gbps PHY, transmitter TJ = 0.35 p-p UI, DJ = 0.17 p-p UI and RJ = 0.08 UI p-p, where UI ranges from 3,200 psec to 320 psec. The receiver TJ = 0.56 p-p UI, DJ = 0.32 p-p UI and RJ = 0.24 p-p UI over the same range of UI. In the JESD204B specification, total jitter is defined the same way.