As NAND flash continues to increase in density and decrease in cost per gigabyte, it has enabled more cost-effective storage. This benefits a wide (and constantly growing) range of digital consumer products. Selecting the most appropriate high performance NAND architecture for any given application is of increasing importance as the ECC requirements for NAND continue to increase. ??This article will explore the attributes of and differences between e-MMC and NAND with built-in ECC (such as Toshiba’s SmartNANDTM) – as well as go into detail about the applications that are best suited for each.
Exhibit A: e-MMC
First up, e-MMC, which stands for embedded multimedia card, is one of the most popular embedded memory solutions. It consists of a number of NAND flash memory devices and a controller in a single ball grid array (BGA) package. It is used in a variety of mobile applications such as: smartphones, digital book readers, and portable terminals. e-MMC is a widely-supported JEDEC standard that uses the HS-MMC (high speed multimedia card) interface and command protocol.
The e-MMC is the embedded (chip) version of the multimedia card. Originally created by Siemens and Sandisk, it has evolved to become one of the most widely available standard non-volatile memory devices for embedded use.
The JEDEC e-MMC standard V4.41 has backward compatibility. Therefore, it is possible to operate a V4.41 compliant device on a V4.3 or V4.4 compliant system. Several security functions such as Secure Erase, Secure TRIM, and RPMB are added to V4.4 compared to V4.3. Moreover, the Hardware Reset Signal and DDR interface became available for V4.4 onward. Furthermore, new functions such as HPI, background operation, write reliability and enhanced reliable write are added to V4.41. The table below is a comparison that shows the differences between JEDEC standards V4.3, V4.4 and V4.41.
Composition of an e-MMC System
An e-MMC system generally consists of a host controller, an e-MMC device, and a HS-MMC driver, which is software that controls the e-MMC (see Figure 1).
The host controller has a host CPU and a HS-MMC interface. The e-MMC also has a HS-MMC interface.
The e-MMC consists of raw MLC NAND flash memory and a controller. The controller has a HS-MMC interface which can be connected to the host controller. It also has a NAND interface which is connected to the raw MLC NAND flash memory. It has several functions such as bad block management, wear leveling and error correction code (ECC), to utilize the raw MLC NAND flash memory efficiently.
The HS-MMC driver handles operations between the host controller and the e-MMC.
Very nice article. You write about asynchronous NAND flash interface with EZ NAND. At first - I`m not engineer, no high school degree in technics (only economic), but I read about solid state discs and their NAND flash. Lower cost NAND are asynchronous (working with ONFI 1.0), higher cost NAND are synchronous (working with ONFI 2.x). Synchronous working like DDR - better speed. So the question is: are EZ NAND memories (ONFI 2.3a, resp. 3.0) support asynchronous interface and that`s the thing why they are lower speeds than synchronous NAND? Thaks for "user" answer.
The design challenges for memory chip designers is ever increasing. This article makes some great points. For more information on the 2012 design challenges from Jedec board memeber in a free video series visit Agilent. www.agilent.com/find/memory_whatisnext