Class D was invented decades ago when there were no power devices to achieve commercially viable performance figures. Sony introduced the first Class D audio amplifier product, the TA-N88 in 1979. It used a power JFET called Vertical FET (V-FET) switching at 500kHz. The FET was not easy to handle as it was a normally-on device. The large input capacitances necessitated a large gate driver stage with To-220 BJTs with heatsink. Yet it demonstrated what Class D can bring to audio amplification.
With today’s state-of-the-art MOSFET technology, a practical power MOSFET can achieve well above 90% power efficiency in the Class D output stage. One simple way to see how the device is close to the ideal power switching device is to take a look at an R*Qg figure of merit (FOM). On silicon technology, on resistance (RDS(ON)) and gate charge (Qg) oppose each other. In other words, the lower the RDS(ON), the higher the gate charge will be, hence slower the switching.
To achieve the highest efficiency in Class D amplifiers, conduction loss from RDS(ON) and switching loss from switching speed dictated by Qg need to be optimized. Figure 2 illustrates how an optimal die size for a given output power is chosen. The minimal power loss is at an optimal die size. As the device technology advances, the total power loss at the optimal point reduces and the die size gets smaller, allowing for better performance and smaller system size
Figure 2: Power MOSFET die size optimization
Improvement in RDS(ON) and Qg FOM indicates the advancements in power MOSFET technology. For example, let’s take a look at the two 100V rated devices that are a couple of generations a part. The IRF540 planer structure from the 1980s has 66m ohms with 55nC of Qg. The latest trench structure MOSFET IRF6665 is a 53m ohms device with 8.4nC gate charge. The FOMs are 3,300 and 445 respectively, showing the latest MOSFET has greater than 7 times better FOM. The newer MOSFET requires much lower gate drive effort to achieve the switching speed, consequently lower switching power loss.
Integrated Class D driver
To form a practical Class D amplifier, there are four essential functions; gate driver, level shifting, deadtime generation and under-voltage lockout protection (UVLO). Each of these functions is complex and involves a mixture of analog and logic circuitries. The high device counts encourages the integration of all four functions into a single IC.
In order to enjoy the benefits of state-of-the-art power MOSFETs, precise control of the gate drive signal is crucial. Stable deadtime control and level shifting to control the MOSFET according to the PWM signal from the modulator section are vital. Deadtime is a major source of non-linearity in Class D amplifiers. Insertion of deadtime increases distortion as it modulates the gain in the Class D power stage as it reduces the duty cycle of each MOSFET.
While motor drive inverters require 500ns to 1us deadtime range, a high-performance Class D amplifier has a stringent deadtime requirement of one tenth of these values. The amount of deadtime is primarily dictated by the switching speed of the MOSFET but in reality a design uses 2 to 3 times the amount of deadtime to deal with propagation variability in the gate driver stage. MOSFETs with better FOA require a smaller deadtime amount from the faster switching speed, therefore, contributing to better linearity.
Robust protection features are as important as the Class D loop controls. Gate driver ICs should offer under-voltage lock-out (UVLO) protection to protect the MOSFETs from operation in the linear mode that can damage them. Other protection features include thermal shutdown and over-current protection.
The nature of the power dissipation source in Class D in an over-loaded condition result from conduction loss from RDS(ON). Monitoring a voltage across the MOSFET while it is in an on state is a good way to sense over-loading conditions. This scheme does not take any additional power shunt device that degrades efficiency and requires a large footprint. A bonus feature from the RDS(ON) based current sensing is that sensitivity of load current detection increases with MOSFET temperature, making the over current protection much more robust.