Around the globe, engineers and technicians using RF power devices have had many concerns regarding the specifications for leakage current, what the specifications mean in terms of the part’s performance in the field, and most importantly, how to properly test/verify that a given part is meeting its printed leakage current specification…
What, specifically, is “Transistor Leakage Current”?
A transistor can be thought of as a simple “ON/OFF” semiconductor device. In an ideal sense then, the transistor only allows DC current to flow through it when it is “ON” (i.e. properly biased and with the proper DC supply voltages applied), and allows zero DC current flowing through it, when it is “OFF.” In reality, a small amount of DC current still flows through all transistors, even when they are in their “OFF” state, as long as the DC supply voltages are applied. This relatively low-level of DC “OFF” current is commonly referred to as transistor leakage current. Leakage current is present in every type of transistor, using any semiconductor technology (Bipolar, CMOS, VMOS, LDMOS, GaAs, GaN, etc.). Note: Leakage current for bipolar junction transistors (BJT) is commonly referred to as ICEO, the collector-emitter cutoff current (base open). This is one reason why you seldom find the words “leakage current’ in older transistor data sheets and data books. With the advent of Field-Effect Transistors (FETs), and the subsequent FET technology advancements (VMOS, LDMOS, etc.), BJTs have decreased dramatically in usage as RF power transistors.
“Normal” leakage current, or the expected amount of leakage current that is within a given part’s specifications, is due mainly to imperfections and limitations in the transistor die. The actual causes of this expected leakage current are beyond the scope of this paper.
Leakage Current Specifications for Transistors
Leakage current is specified today in virtually every transistor data sheet. For the most part, though, the leakage current specifications are rarely noticed, and are almost never a cause for concern by RF power design engineers. This is because leakage current is typically very low, usually in either the low µA (micro-amps, or 10-6 amps) range or even the nA (nanoamps, or 10-9 amps) range. Since leakage current is so low, it is only considered “design-impacting” when:
A Specific Example for Leakage Current Specification
- The transistor is used in extremely low power applications; or,
- In rare cases, the transistor is used in designs where extremely tight bias current limitations exist; or,
- In some cases, a given transistor unit in the field is found to be “out of specification” with regard to its published leakage current specification.
For field effect transistors (FET), leakage current is usually specified for both drain-to-source current (IDSS) and for gate-to-source current (IGSS), as in this excerpt from an actual data sheet:
Fig. 1: Example of leakage current specifications for FET device. (Click on image to download hi-res PDF).
Notice that the specifications for leakage current are dependent on certain conditions of the transistor device under test (DUT). In the example above, “Table 5” includes the device’s electrical characteristics, all to be tested at a case operating temperature of TC = 25° C (unless otherwise noted). The Zero Gate Voltage Drain Leakage Current, IDSS, is specified twice as a maximum value, with two different drain-to-source voltages (VDS = 66 VDC and VDS = 28 VDC). In each case the gate-to-source voltage is specified at zero volts (VGS = 0 VDC), i.e. the gate and the source of the DUT are shorted together to properly test IDSS. “IDSS Max,” or the maximum allowable value for drain leakage current, is clearly specified for this device as up to 10 times higher with VDS = 66 VDC than it is with VDS = 28 VDC. Gate-Source leakage current, IGSS, is specified once, with VGS = 5 VDC and VDS = 0 VDC, which means the drain and the source of the DUT are shorted to test IGSS.
Key starting point: In order to determine if the leakage current on an actual device is within its own printed specification, care must be taken to reproduce the proper testing conditions.
Fig. 2: Always use proper test conditions and calibrated methods/procedures.