Editor’s Note: This article first appeared in the Summer 2011 issue of Xcell Journal, and is reproduced here with the kind permission of Xilinx.
Today’s complex FPGAs contain large arrays of functional blocks for implementing a wide variety of circuits and systems. Examples of such blocks are logic arrays, memory, DSP blocks, processors, phase-locked loops (PLLs), and delay-locked loops (DLLs) for timing generation, standard I/O, high-speed digital transceivers and parallel interfaces (PCI, DDR, etc.). Often, these FPGAs use multiple clocks to drive different blocks, typically generating them using a combination of external oscillators and internal PLLs and DLLs. The system designer has to decide how to combine external and internal resources for optimal clock tree design.
Programmable clock oscillators offer a number of advantages when used as timing references for FPGA-based systems. Chief among them is the design flexibility that arises from high-resolution frequency selection for clock tree optimization. Another big benefit is spread-spectrum modulation for reducing electromagnetic interference (EMI).
A silicon MEMS clock oscillator architecture that is inherently programmable solves many problems for system designers who use FPGAs. The architecture of this type of microelectromechanical system can easily incorporate additional features such as spread-spectrum clocking for EMI reduction and a digitally controllable oscillator for jitter cleaning and fail-safe functions in high-speed applications.
A typical system needs a number of clock frequencies. Some are standard, either because they are mandated by an industry specification – for example, 100 MHz for PCI Express – or by virtue of being used widely, such as 75 MHz for SATA or 33.333 MHz for PCI. Such frequencies are associated with I/O interfaces to ensure interoperability, because the two sides of the interface may not belong to the same system. In contrast, the user may select the clock frequency for driving processors, DSP and state-machine engines to optimize for speed, power or resource usage.
When optimizing for speed, you should clock the processing engines with the highest clock frequency to maximize the number of operations per second. However, the clock period jitter must also be low to ensure the minimum clock period is greater than the critical timing path in the design; otherwise logical errors may occur. A common approach for frequency selection is to use internal FPGA PLLs to synthesize a higher-frequency clock from a standard external reference oscillator. This approach is effective if the internal PLL has high-frequency resolution and low jitter.
Some FPGAs incorporate internal, low-noise fractional PLLs that meet all of these requirements. In this case, you can use a simple external oscillator reference. However, in many cases, FPGAs use PLLs with a ring VCO and integer feedback dividers to synthesize different frequencies. Such PLLs are small and flexible, relatively easy to design and control, and consume very little power. But when using these internal PLLs, it is difficult to achieve high resolution and low jitter simultaneously.
Figure 1. Block diagram of a typical integer PLL
The general architecture of an integer PLL is shown in Figure 1. The PLL output frequency is programmed with a combination of predivider (P), feedback divider (M) and postdivider (N), as in the equation below:
The PLL feedback loop forms a band-limited control system. The output period jitter depends mostly on the reference clock phase noise (PNin
) and the internal VCO phase noise (PNVCO
), as formulated here:
As related to the output phase noise, the input reference and VCO phase noise contributions go through low-pass and high-pass filter responses, Hin
respectively. The cutoff frequencies of HVCO
are directly related. Figure 2 illustrates how Hin
relate to each other in an exemplary second-order PLL.
Figure 2. Phase noise transfer function examples for
input and VCO, using a second-order PLL
The maximum PLL bandwidth depends on the phase detector update rate. In most practical PLLs, the maximum practical limit is as shown below:
For example, if the PLL input frequency is 40 MHz and P=40, the maximum practical PLL bandwidth will be 100 kHz.
The period jitter is related to phase noise by a sine filter response, as shown in Figure 3.  As you can see, period jitter is more sensitive to overall PLL output phase noise at frequency offsets closer to fout
/2. Since the PLL bandwidth is significantly smaller than fout
/2, the reference clock typically makes a small contribution to the period jitter while the internal VCO phase noise contributes more.
Figure 3. The filter response spectrum
relating phase noise to period jitter
The higher bandwidth of the PLL reduces the contribution of the internal VCO to output period jitter and yields lower overall period jitter. In most cases, it is desirable to set the bandwidth higher to reduce the internal VCO noise and improve jitter. On the other hand, achieving high-frequency resolution requires larger values of divider P, which limits the maximum PLL bandwidth. This conflict imposes a trade-off between high resolution and low jitter. Use of an external high-resolution oscillator alleviates this trade-off by moving the burden of the high resolution to the external reference.
High-performance programmable oscillators, such as those available from SiTime (www.SiTime.com
), are an example of such devices. With these types of oscillators, the internal PLL only needs to support very limited frequency synthesis functionality, which allows higher bandwidth and less jitter.
Another advantage of programmable external reference oscillators is the ability to select a higher-frequency reference. This allows higher-bandwidth internal PLLs, which yield lower jitter. For example, an application may require a 56-MHz clock with 10-picosecond RMS period jitter to meet timing requirements.
Figure 4 shows two ways of obtaining a 56-MHz clock. The first uses a standard 25-MHz reference and the second one uses a nonstandard 28-MHz reference. The first method requires a large predivide ratio to achieve the required resolution, but leads to higher output jitter. The second method minimizes the P value and allows higher PLL bandwidth, leading to lower output period jitter.
Figure 4. (a) Lower PLL bandwidth, higher jitter architecture;
(b) Higher PLL bandwidth, lower jitter architecture
Most programmable oscillators use a resonator element and one or more PLLs to synthesize different frequencies. Traditionally, quartz crystals have been the choice for stable resonators. However, packaging challenges have limited the availability of such programmable oscillators. More recently, silicon MEMS oscillators have arrived on the market, offering a cost-effective combination of stable resonators and high-performance PLLs in a number of industry-standard small packages. These oscillators provide an attractive solution for FPGA clocking for optimizing the clock tree in FPGA systems. Such clocks also meet the requirements for more stringent jitter specifications of high-speed transceivers. EMI reduction
Once a stable resonator pairs up with a high-performance synthesizer in a programmable oscillator, many other useful clock features become easily accessible. One example is spread-spectrum clocking (SSC) for EMI reduction.
The SSC oscillator is a clock whose frequency is modulated to ensure the energy of the clock signal is spread over a larger frequency range, hence reducing overall peak electromagnetic radiation within a given frequency range. SSC is especially useful in FPGA-based systems because it reduces EMI from all circuits and I/Os that share the same clock source. By contrast, trace filtering and rise/fall control methods tend to decrease EMI in certain sections of the system. Figure 5 shows how SSC reduces peak EMI radiation.
Figure 5. Spread-spectrum clocking modulation to reduce peak EMI radiation
The important parameters in SSC are modulation range and modulation method (center-spread or down-spread). Some programmable oscillators, such as the SiT9001 from SiTime, provide a wide selection of SSC modulation range, from 0.5 percent to 2 percent in both down-spread and center-spread flavors. This menu election allows designers to optimize the SSC for the best system performance while minimizing EMI. 
Another example of a useful feature that fractional-N PLLs in programmable oscillators enable is digitally controllable oscillators. The DCO is a powerful feature for implementing low-bandwidth, fully digital PLLs with FPGAs for fail-safe, holdover or jitter cleaning in high-end telecom and networking systems. The silicon MEMS advantage
New silicon MEMS oscillators have expanded the portfolio of commercially available programmable oscillators significantly over the last several years. These oscillators enable the user to customize the reference frequency for optimal clock tree design by choosing the best combination of external reference and the FPGA’s internal PLL parameters. Additionally, designers can easily select power supply voltage, package, temperature range, frequency stability and drive strength to match the application needs. The programmable aspects of these oscillators also reduce lead time and allow rapid prototyping and fast production schedules.
SiTime’s single-ended and differential silicon MEMS oscillators already reside on some Xilinx demo boards (see Table 1). These parts can be ordered for different frequencies, voltages and packages for optimal system performance.
Table 1. SiTime programmable devices on Xilinx FPGA demo boards
 Mike Li, Jitter, Noise, and Signal Integrity at High-speed, Prentice Hall, 2007
 SiTime, “Phase Noise and Jitter Requirements for Serial I/O Applications,” application note AN 10012
 Sassan Tabatabaei, Clocking Strategies for EMI Reduction, Interference Technology – EMC Test and Design Guide, November 2010About the author
Sassan Tabatabaei is Director of Strategic Applications at SiTime Corp. (www.SiTime.com
). Sassan can be contacted at firstname.lastname@example.org
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