PCI Express includes many features that can be taken advantage of by high-speed protocols such as IEEE 1394b (FireWire) to provide benefits to the consumer: increased bandwidth and more efficient performance, reduced board footprint, improved power management, increased error immunity and support for a long list of feature enhancements.
The significant benefits that PCI Express offers over conventional PCI bus architectures can enable designers to develop the most robust possible networking solutions using the FireWire standard. Among the most significant are bandwidth and efficiency improvements of more than 30 percent as shown on the screens in figure 1.
Fig 1: PCIe with FireWire shows 30 percent improvement in efficiency as compared with PCI. The screen above is PCI; the one below is PCIe.
PCI supports a maximum of1 Gigabit/sec bus throughput, slightly above the 800 Mbit/second bandwidth requirement of 1394b. Since PCI allows for multiple devices to reside on the same bus segment, 1394 traffic will essentially utilize all the bus bandwidth and any additional device on the bus will saturate the bus.
Typical 1394 applications such as streaming video requires additional high speed traffic such as graphic data transfer that will compromise video display performance. PCI Express both increases the link bandwidth to 2.5 Gigabit per lane per direction for PCIe gen1, 5 Gb/s for PCIe gen2, and PCIe gen3, 8 Gb/sec bandwidth, which is even more useful due to the elimination of 8b/10b coding. As a point-to-point protocol PCIe prevents other traffic from competing with IEEE 1394 traffic.
Efficiency is another limiting factor in PCI bus performance because of its transaction termination protocols. An initiator may constantly retry the bus, which increases bus overhead, and limits bus performance even further. If a 1394 controller and a graphics controller reside on the same PCI bus segment both devices constantly compete for bridge resources, which may result with a live lock condition.
PCI Express replaced the PCI retry termination with a split transaction protocol which eliminates the need for transaction termination on retry; lengthy negotiations and removes all wait states therefore resulting with significantly better link utilization. With PCI Express, credit-based flow control eliminates hierarchy traffic congestion at the system level. A virtual channel is established within the fabric so that neither device will initiate a request unless resources available within its dedicated virtual channel.
In addition to the above protocol enhancements PCI Express, as a serial protocol, offers significant system board design simplification and resultant reduced cost. PCI Express eliminates the burden of supporting 32-bit or 64-bit wide address and data buses required for PCI. System boards that are solely PCI Express based can now be reduced to 4 layers only and placement and routing of the board becomes much easier, which makes routing high speed 1394 differential pair signals easier.
Fig 2: PCIe enables significant efficiencies in board utilization, below right, compared with PCI, shown by the board above.
PCI Express-based 1394 host controllers can now be supported in much smaller packages and allow placing multiple controllers on a single PCI express system board, as shown in figure 2 - right and below. The 10x reduction in trace routing enabled by PCI Express also allows more freedom in the placement of the 1394 connector resulting from easier routing the PCI Express and1394 signals.
PCI Express enhances power savings compared to PCI by allowing not only software controlled power states, but activity based Active State Power Management (ASPM) which saves power at run time without software intervention. PCI Express gen2 allows for level margining, which optimizes power based on channel quality, and gen3 introduced dynamic equalization, which optimizes signal integrity and power efficiency at the same time.
For mobile platforms PCI Express offers an integrated hot swap solution that eliminated the need for a dedicated controller such as the card bus controller needed for a PCI based mobile architecture. Operating System support for multiple 1394 host controllers is provided through the IEEE 64-bit serial number supported by PCI Express that uniquely identifies each controller and is currently required by the Vista operating system.
Utilizing PCI Express based 1394 host controllers brings Reliability, Availability and Serviceability (RAS) features to 1394 system design. PCI Express requires standard on-chip hardware for error detection, correction and reporting that is not required in PCI.
Robust multi-level error reporting and correction architecture allows correctable errors to be handled on the fly without system software intervention, non-fatal errors to be corrected by software and only fatal errors cause interruption of normal operation in extreme cases.
Error reporting is standardized by the specification and eliminates the need for an extra software driver to handle vendor proprietary error mask bits, which minimizes software support for 1394 products. By comparison, PCI based host controllers could only detect simple parity errors.
In addition to all the features and benefits detailed above, PCI Express includes features that have yet to become productized benefits for the consumer. These features include: support for virtualization; latency tolerance reporting (LTR); optimized buffer fill/flush (OBFF); support for 64-bit 1394 open host controllers (OHCI) and simplified support for multiple 1394 host controller system solutions. Simply stated, PCI Express based host controllers are “future proofed.”
About the author:David Thompson is a Distinguished Engineer in the Systems Applications Engineering area at LSI Corporation. He has an MSEE from Stanford University, is a Senior member of IEEE and has been with Bell Laboratories and its inheritors for 31 years before becoming LSI Corporation. His group is currently developing 1394, USB and other serial-bus technology standard products for LSI. He
is also serving his tenth year as a member of the 1394 Trade
Association’s Board of Directors and is Chair of the 1394 TA
Qualification Review Board.
If you found this article to be of interest, visit the Micocontroller Designline
where you will find links to relevant technical articles, blogs, new products and news.
You can also get a weekly newsletter highlighting the latest developments in this sector - just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register.