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re: 3D IC Design
docdivakar   9/19/2011 4:48:46 PM
@Samta: good article! You are right in your comment, 3D stacked IC design and its 2.5D variant do not require a radically different 3D-enabled design environment. But they do need 'enablement' of some basic features including 3D editors and simulations including thermal and emag. How ever, I take exception to some points you make in the article: 1. RDL's are not typically formed on the backside of the die (you need to quote the proces flow here if you want to be specific). This depends on whether the fab is providing the RDL or the backend fab / packaging house is providing it. Most existing flipchip processes do backend metallizations including RDL on the TOP side of the dice! 2. 1-um TSV has ways to go! 3. 3D floor planning and partitioning is easier said than done. The chip-package co-design that you mention has to be much earlier in the design flow and has to be tightly coordinated. Dr. MP Divakar

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David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.