One of the challenges engineers often encounter while designing a practical and reliable powertrain drive is the existence of high common mode noise. Common mode noise (also known as dV/dt noise) is generated naturally within a system when there is high frequency switching between high voltage supplies. This article will discuss the possible sources of dV/dt noise in a hybrid powertrain drive and suggest solutions to the problem.
Sources and effects of powertrain drive common mode noise
A typical block diagram of a hybrid powertrain drive is shown below. When the gate drivers switch the high side and low side IGBTs (insulated gate bipolar transistors) in sequence, high dV/dt noise is generated. For example, a typical powertrain connected to a high voltage 400 VDC with the switching rise and fall time of 50 ns, will generate dV/dt noise of 400V/50 ns ~ 8 kV/µs whenever the gate driver switches.
When faced with short circuit conditions due to faults, additional overshoot voltage (V=L*di/dt) will add on to the DC rail voltage. This additional overshoot voltage is caused by large short circuit current transient (di/dt) flowing through the circuit stray inductance, L. The gate driver circuit must be capable of handling this additional dV/dt noise so as to maintain control and execute the correct protection protocol.
Additionally, the need for higher DC rail supply voltage for larger hybrid vehicles, such as trucks and buses, and the need for faster switching frequency to reduce conduction loss, have increased system requirements for higher dV/dt noise rejection. Normally, having a hybrid powertrain drive with dV/dt noise rejection of 15kV/µs is essential to maintain overall system performance, reliability, and robustness.
When dV/dt noise couples through parasitic capacitances within the system and causes undesired voltage transition, it becomes a serious threat. It may eventually cause the system to lose control, i.e. arm short, false feedback, etc. Although dV/dt noise is very much undesired, it exists naturally within the powertrain drive as explained earlier. Designers have no choice but to identify and tackle all possible coupling paths of dV/dt noise. The figure below illustrates the possible parasitic capacitance paths existing within a system.
Solutions to parasitic capacitance
To provide adequate rejection for common mode noise, designers have to tackle the aforementioned parasitic capacitances within the system.
First of all, designers should aim to minimize the gate driver external/layout parasitic capacitance through efficient layout design. It is essential to maintain sufficient isolation spacing between the two adjacent low voltage and high voltage regions of the circuit board. Insufficient spacing will reduce the effective isolation and increase parasitic coupling, which will degrade common mode rejection performance.
Additionally, high impedance signal lines that are more sensitive to dV/dt noise (i.e. VIN+, VIN- and DESAT pins of the ACPL-38JT
optocoupler in the figure below) should be kept as far away as possible from the adjacent isolated region to avoid parasitic coupling. It is always recommended to place bypass capacitors close to the driver supply pins to keep the supply current loop as small as possible and minimize the stray inductance coupling by common mode transient current. The figure below shows the comparison between a dV/dt sensitive layout (top) and a recommended layout (bottom) using the ACPL-38JT optocoupler.
Secondly, designers should address the Miller capacitance coupling. When dV/dt noise couples through the Miller capacitance during switching, it will induce transient noise current. This transient noise current will flow through the stray inductance existing along the layout paths from the IGBT gate to the gate driver, and it will affect the gate control voltage. To minimize the effect of dV/dt noise through the Miller coupling and to provide cleaner switching waveforms, designer should keep the IGBT gate charging and discharging loop as small as possible. An example of a gate driver current buffer circuit to the IGBT is shown below (top), and a recommended layout is shown at the bottom.