The demand for embedded non-volatile memory (eNVM) in system-on-chip (SOC) designs has grown exponentially in recent years as newer applications evolve in communications and consumer electronics. The memory content of complex SOCs has increased due to more sophisticated firmware and software demand on rich application features. Embedded flash (eFlash) memory is highly desirable in most applications to store critical data and code due to its robust endurance. In addition, eFlash enables field programming that provides great flexibility for last minute system level changes.
eFlash technology usually tracks behind the baseline logic technology ramp-up by about three years and mainly aims for second wave applications; therefore, in addition to real flash reliability, an ideal eFlash technology should have the following features:
- Simple integration into Logic baseline process leads to fewer masks, low manufacturing cost
- No change to baseline Si models, which means existing design IPs are preserved ? re-use IP, time to market
- Compatible with existing transistors
- High intrinsic yield and easy to test
- Allows both Flash and EEPROM on the same chip
Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory technology has all the above features and is ideally suited for eFlash. SONOS or Charge Trap Memory Technology
A SONOS memory device uses an insulating layer, such as silicon nitride, with traps as the charge storage layer. The traps in the nitride capture the carriers injected from the channel of a MOS transistor and retain the charge. This type of memory is also known as charge trap memory. Since the charge storage layer is an insulator, this storage mechanism is inherently less sensitive to pinhole defects, and it is more robust in terms of yield and data retention.
SONOS memories have very few “weak” bits, and this makes testing simpler. Another key advantage of SONOS technology is the relatively low voltages required for program/erase as compared to Floating gate memory. The 65-nm SONOS technology demonstrated is based on F-N tunneling for both program and erase, which dramatically improves the endurance, compared to using hot electron injection (HEI) for programming.
65nm SONOS technology integrates a highly reliable SONOS transistor into the existing 65nm CMOS process flow with only three additional masking layers. It has a low thermal budget, which has minimal impact on the electrical parameters of the existing CMOS FETs. The SONOS transistor shares many of the key process steps with the CMOS transistors. Therefore, many regions of the SONOS transistor, such as source, drain, and gate, are identical to those of the CMOS transistors. This makes the process architecture of the embedded SONOS technology simple. The 65nm SONOS technology uses low program and erase voltages. Hence the flash macro utilizes existing core and I/O gate oxides and no additional high voltage gate oxide is required. Fig.1: Schematic (top) and TEM cross section (bottom) of SONOS FET
A transmission-electron-microscopy (TEM) cross section of an actual SONOS transistor integrated into 65 nm baseline process is shown in Figure 1.The schematic is a SONOS transistor that is fabricated using a typical foundry logic CMOS process flow. The device has salicided gate, source, and drain regions and the gate stack is made up of salicided polysilicon. The embedded SONOS technology typically offers multiple cell options to fit into different application, without compromising reliability. The program speed is 1 to 5 ms and erase speed is 5 to10 ms depending on application options and macro architecture. The same cell can be used for Flash and EEPROM.