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Addressing the new challenges of ASIC/SoC prototyping with FPGAs

10/12/2011 05:04 PM EDT
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2006ashok
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re: Addressing the new challenges of ASIC/SoC prototyping with FPGAs
2006ashok   10/26/2011 12:25:22 AM
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Ashok: This is a very important consideration when developing a FPGA based prototyping. You would want to leverage or re-use the infrastructure created while testing your design on the FPGA prototype, as much as possible during ‘ASIC bring up’. The prototyping test infrastructure can be categorized into: (1) Hardware interface or Target interface – this includes everything the design under test – DUT (‘design prototype’) interfaces to external devices, and daughter boards in the context of the system. (2) Test benches: This may be the a self-running firmware/synthesizable test-bench on the hardware or test suites, such as TLM or C-API that reside in a workstation in co-modeling environment. Both items noted in (1) and (2) implemented when prototyping can be re-used when you begin testing actual silicon. Build the ASIC reference board for the actual ‘Silicon testing’. Bring out all I/Os of the ASIC to the connectors. These connectors must be mechanically and electrically compatible to the prototyping board that you plan to use. For example if you use S2C TAI LM the TAI LM mounts on the reference board. In the prototyping stage you would connect all the interfaces to the ‘prototyping system’ including any PHY interfaces modeled as daughter cards that eventually gets replaced as a sub-set of the ASIC test chip. When you get actual ‘silicon’ in hand you would simply insert/mount into the reference board. The main point to realize here is that the target interface to the actual ‘silicon’ remains the same as the one used during prototyping. If you desire to create additional reference boards for early customer use you may re-design the reference design without the connectors that are routed and the corresponding signal routing. For additional information please contact S2C Inc., www.s2cinc.com

DrFPGA
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re: Addressing the new challenges of ASIC/SoC prototyping with FPGAs
DrFPGA   10/20/2011 6:41:49 PM
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My main question is about the amount of infrastructure design work that needs to be done and if it can be leveraged during the ASIC bring-up effort. I don;t mind development if it needs to be done later anyway, but developing a test platform twice seems like alot of extra work.

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