Field-programmable gate arrays (FPGAs) are a valuable technology for designing and prototyping digital logic into today’s applications. However, high FPGA unit cost can sometimes prohibit higher volume production. Several alternatives exist for transferring a digital design, implemented with an FPGA, into higher-volume production. Low-cost solutions such as structured application-specific integrated circuits (ASICs), cell-based ICs, and gate arrays offer higher performance, lower power consumption, higher levels of integration, and better response to radiation effects. The idea of migrating an FPGA design into an ASIC can be overwhelming to a design team, but careful planning and partnering with an experienced ASIC vendor can significantly ease the process.
Designing a new product in an FPGA allows for design modifications to be made quickly in hardware. Once the design code is stable and the product is ready for production, a migration from an FPGA to an ASIC can cut the production unit cost by up to 50%. The low non-recurring engineering (NRE) charges associated with a mid-range ASIC solution coupled with a much lower unit price point make this strategy a powerful tool in achieving low overall expense, giving users a competitive cost advantage in the market.
To help ease the migration process, designers must consider several items during the initial design phase:
- Today’s designs are larger, more complex, and contain more specialized intellectual property (IP) than ever before. Careful selection of IP early in the design phase is essential.
- Developing the FPGA and ASIC in a parallel design flow will help speed up the migration process.
- Planning for portability to an ASIC from the beginning will help shorten the time to market and decrease development cost.
- Good coding practices such as the use of synchronous design techniques will enable the architecture to be ported across many different technology platforms.
- Documentation is essential. If a little time and effort is used in the early stages of the design, the migration will require minimal engineering resources.
The migration can result in a drop-in replacement alternative that is footprint compatible to the FPGA. If the system can tolerate packaging and footprint flexibility, designers can attain further cost reduction.
Complex systems may require several FPGAs to prototype a complete system-on-a-chip (SoC) design. ASICs offer better gate density than FPGAs, as well as better core performance. This allows multiple FPGAs to be combined into a single SoC ASIC, saving expensive board real estate. If the architecture will not allow for full integration, a multi-personality ASIC can be produced to emulate the different FPGAs, allowing for a direct functional drop in replacement. This will optimize cost savings by reducing the ASIC tooling charges.Parallel design flow
Parallel design flows allow the designer to compress the ASIC development schedule (see figure 1). Prototyping in an FPGA enables engineering teams to verify functionality prior to ASIC implementation. It also provides a path for early hardware and software validation. In this design flow, the register transfer level (RTL) is developed and targeted to the FPGA and provided in parallel to the ASIC vendor for review and analysis. This allows the ASIC vendor to offer recommendations and modifications to the code to enhance robustness. Timing scripts and clocking architectures are developed for both the FPGA and ASIC. Package selection for the ASIC is determined along with signal integrity and power dissipation analysis. The printed circuit board (PCB) can be developed at this time to handle the larger power-hungry FPGAs with an identified path for migration to a smaller, more efficient ASIC package.
Figure 1: In a parallel design flow, the RTL is developed and targeted to the FPGA and simultaneously provided to the ASIC vendor for review and analysis.
One option is to place the ASIC design on hold pending the final FPGA verification, or ramp-up to production. More commonly, the ASIC team begins logical design activities once the base architecture is fixed, IP requirements are defined, and pin out is fixed. Early ASIC development may also include development of the design for test (DFT) structures, script development for static timing analysis (STA), initial floor planning, and cell placement. Any major changes to the design can be quickly evaluated in the ASIC flow to ensure that the scripts for DFT and timing do not require modification. The final timing convergence and physical design flow wait until the design is ready to move to the ASIC.