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Using the clock period constraint to your advantage

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Sharad Sinha
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re: Using the clock period constraint to your advantage
Sharad Sinha   3/31/2012 4:33:51 PM
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Yes Max, such contributions do help a lot in understanding tool flows etc. in a much better way.

Max The Magnificent
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re: Using the clock period constraint to your advantage
Max The Magnificent   12/1/2011 2:39:44 PM
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What? A standard? But if it was easy, everyone would be doing it (grin)

an_m
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re: Using the clock period constraint to your advantage
an_m   12/1/2011 8:46:51 AM
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what strikes me, as I move between Xilinx to Altera to Lattice designs, is they all have different constraint systems. they all have the same basics, clock period, set up and hold times to constrain, lets have a common system in place please,

Max The Magnificent
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re: Using the clock period constraint to your advantage
Max The Magnificent   11/30/2011 6:13:44 PM
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I know that this particular article is Xilinx-centric, but it's still jolly useful information, and I for one would welcome similar (short, sharp, focused) contributions on tricks and tips relating to any vendor's tools...

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