The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due to ASIC design complexity. To overcome the risk of re-spins, high NRE costs, and to reduce time-to-market delays, it has become very important to design the first time working silicon.
This chapter constitutes a general set of recommendations intended for use by designers while designing a block or an IP (Intellectual Property). The guidelines are independent of any CAD tool or silicon process and are applicable to any ASIC designs and can help designers to plan and to execute a successful System on Chip (SoC) with a well-structured and synthesizable RTL code.
The current paradigm shift towards system level integration (SLI), incorporating multiple complex functional blocks and a variety of memories on a single circuit, gives rise to a new set of design requirements at integration level. The recommendations are principally aimed at the design of the blocks and memory interfaces which are to be integrated into the system-on-chip.
However, the guidelines given here are fully consistent with the requirements of system level integration and will significantly ease the integration effort, and ensure that the individual blocks are easily reusable in other systems. These guidelines can form as a basis of checklist that can be used as a signoff for each design prior to submission for fabrication.
The book preface can be found here.
This week we start with Chapter 2 Part 1 which includes:
2.2 Synchronous Designs
2.2.1 Avoid Using Ripple Counters
2.2.2 Gated Clocks
2.2.3 Double-Edged or Mixed Edge Clocking
2.2.4 Flip Flops Driving Asynchronous Reset of Another Flop
Part two will be presented next week.
is a Senior Systems Engineer with Freescale Semiconductor. Since
joining Freescale in 2005, he has been responsible for IP/SoC
Architecture and has led the design and development of various SoCs for
multimarket segment. As a systems engineer, he has been involved in
product definition and writing specifications, MCU/MPU-based products
for the mid-high end industrial and consumer market space. Prior to
joining Freescale, he worked for Agilent Technologies, ST
Microelectronics and DCM Technologies as a design engineer and lead,
focused on printing ASICs, USB2.0 PHY, PCI-Express, Infiniband and
Serial ATA protocols.
He earned a Bachelor’s degree in Electronics
and Communication Engineering from Netaji Subhas Institute of Technology
(NSIT), India in 2000, has more than 30 publications in international
magazine and holds a patent on serial links. You can visit his website here.
If you are interested in purchasing the book, it is available from Amazon