In phase-change memory (PCM) low-field electrical resistance is typically used to quantify the programmed cell state. However, this metric has several disadvantages. First, it exhibits temporal drift, which is a significant challenge for realizing multilevel PCM. Moreover, because of cell-geometry effects, this metric saturates after a certain point and thus masks the fact that the amorphous size increases with increasing input power. Finally, the resistance is typically measured as the current for a fixed bias voltage, which adversely affects the signal-to-noise ratio at high resistance values. A new metric for the programmed state in a PCM cell is proposed that has significant advantages over the resistance metric in all these aspects and is more representative of the fundamental programmed entity, which is the amorphous/crystalline phase configuration in the PCM cell. Analytical and experimental results are presented that demonstrate the efficacy of the proposed metric.
Phase-change memory (PCM) is one of the most promising candidates for next-generation non-volatile memory technology [1,2]. The cross-sectional tunneling electron microscopy (TEM) image of a mushroom-type PCM cell is shown in Figure 1 (a) . The cell consists of a layer of phase-change material, such as germanium antimony telluride (GST), sandwiched between a bottom and a top electrode. In this architecture, the bottom electrode has a radius (denoted as rE ) of approx. 15 nm and is fabricated by sub-lithographic means. The top electrode has a radius in excess of 100 nm and the thickness of the phase change layer is approx. 100 nm. A transistor or a diode is typically employed as the access device.
FIG. 1. (a) Cross-sectional TEM image of a PCM mushroom cell. (b) Schematic of a PCM mushroom cell. (c) Approximation of the a-GST geometry. (d) Cylindrical approximation of the a-GST geometry.
The GST is in the crystalline state prior to operation of the device. By application of programming pulses (voltage or current) and the subsequent Joule-heating-induced melting and quenching process, amorphous GST (a-GST) regions are created within the crystalline GST (c-GST) volume as shown in Figure 1(a) and 1(b). By varying the amplitude of the programming pulse, the size of the amorphous region and its thickness (uA) can be increased or decreased in a continuous manner, and this is the basis for multi-level storage in PCM .
FIG. 2. A typical experimental I-V characteristic corresponding to a PCM cell showing the threshold switching behavior and sub- threshold conduction.
In PCM, the electrical resistance of the cell is used to measure uA. As c-GST has much lower resistivity than a-GST, the electrical transport is dominated by the amorphous region. A typical I-V characteristic corresponding to a PCM cell programmed to a certain amorphous thickness is shown in Figure 2. The resistance of the a-GST region varies as a function of the electric field and hence the bias voltage.
Moreover, beyond a critical electric field, the resistivity drops to a very low value, so that a large current flows through the cell, dissipating significant power and thus potentially changing the amor-phous/crystalline phase configuration. This drop in resistance is known as the threshold switching phenomenon [5,6], and has to be avoided when measuring the resistance of a PCM cell as it may disturb the cell state. To measure the resistance, the PCM cell is typically biased with a constant read voltage (VR) that corresponds to the sub-threshold regime.
Because of the field-dependent nature of threshold switching, the threshold switching voltage is different for different programmed states and hence it is not possible to apply a high bias voltage to measure the electrical resistance for every state. Therefore, a low read voltage is typically used, and hence the most common cell-state metric is the low-field electrical resistance. This metric however has several undesirable traits that pose significant challenge to the realization of multilevel PCM.
This is a condensed version of the original article, which is posted on the Journal of Applied Physics website. The rest of the paper covers low-field resistance metric, alternate cell-state metric, experimental results, conclusions, and references.
Are the authors of this paper serious, when they introduce the precision measurement of time into the complexities of sensing in a phase change memory (PCM) array? They acknowledge the problems with this drift metric, capacitance; for which they proceed to offer a solution by adding a further level of complexity for compensation. I assume this compensation would also need to include the effects of temperature. There is a dearth of measurements at elevated temperature and with write/erase lifetime in this paper.
The simplifying structural assumptions made at the start: the hemispherical bottom electrode and equating the dome to a flat surface, are proven by equation fitting from what appear to be device measurements at a single temperature.
While this new drift metric might offer an interesting analytical tool for probing the internal structures of PCM devices for those without the analytical resources of IBM- I for one am not convinced it will amount to anything more than that in relation to commercial PCM products.
It would be more interesting if IBM would devote some of their resources, as they do in their fig 1(a), for a single level, to an actual cross section of the dome in each of its four multilevel states. That would avoid the need for invoking some mysterious crystal filaments to explain anomalies. I would suggest that as the set current is reduced they should pay attention to the shape of the dome, especially along the dielectric surface adjacent to the bottom electrode.
On the subject of scaling, again from figure 1, it is interesting that for a 15nm diameter electrode the width of the dome is 45nm, suggesting that in an array the nearest neighbors center-line must be at the very least 45nm away, questioning the advantage of the multilevel cell over the single level cell.
Join our online Radio Show on Friday 11th July starting at 2:00pm Eastern, when EETimes editor of all things fun and interesting, Max Maxfield, and embedded systems expert, Jack Ganssle, will debate as to just what is, and is not, and embedded system.