Today’s tactical and commercial software-defined radios must have the flexibility and processing power to support a growing number of wideband and broadband waveforms including an extensive library of legacy waveforms. This paper steps through a project that used the secure Xilinx® Zynq™-7000 Extensible Processing Platform (EPP). The single-device platform features a high-performance processing system that leverages ARM® technology, and it provides a large programmable logic unit that supports partial reconfiguration and the Xilinx Isolation Design Flow.
Let’s take a closer look at a software-defined radio (SDR) project built on the Zynq-7000 EPP, focusing special attention on how to utilize the partial reconfiguration and Isolation Design Flow capabilities of the programmable logic unit to support various waveforms, reduce part count and save power. The Zynq-7000 EPP can cut the parts count for our example design from five devices to one, while providing the flexibility to support future waveforms using the same hardware platform.
Figure 1 shows an example block diagram of a tactical SDR. As you can see, the plain-text portion of the radio (sometimes referred to as the “red” side, since the information could be classified) contains a general-purpose processor (GPP) and “red” FPGA. The plain-text information is then encrypted and transformed into cipher text. The “black” side of the radio—which contains a “black” FPGA, another GPP and a modem FPGA for waveform processing—then processes the cipher-text information. To ensure the security of the information, the design isolates and separates the plain-text and cipher-text portions of the radio to prevent an information leak of classified or sensitive data out of the system in plain text. Figure 1 – Block diagram of an example software-defined radio showing the “red” (for classified information) and black FPGAs (click figure to download larger PDF)
Therefore, a typical SDR implementation may use three different FPGAs as well as two separate GPPs, making the device count for these functions as high as five. Designers must size the modem FPGA appropriately to process all of the various waveforms the radio supports. The modem is often required to have all the functions available simultaneously even if only one is needed at a time. For example, processing the Soldier Radio Waveform needs roughly 120K logic cells, 8 Mbits of RAM and 800 DSP slices, while the Mobile User Objective System waveform requires more than 200K logic cells, 10 Mbits of RAM and 900 DSP slices, requiring the modem FPGA to be quite large. Also, the red FPGA in the crypto block must also be large enough to contain all of the various cryptographic algorithms for the associated waveforms. The required number of devices, the amount of I/O signaling between them (which increases power dissipation) and the high logic density of the devices (which increases static current) make this a nonoptimal solution in terms of size, weight, power, and cost (SWAP-C).
With the Xilinx Zynq-7000 Extensible Processing Platform, the modem FPGA, black FPGA, red FPGA, red GPP and black GPP can all be combined into one device, as Figure 2 shows .
Figure 2 – The Zynq-7000 EPP integrates multiple FPGAs into one device for a simple tactical SDR. (click figure to download larger PDF)
The Xilinx Zynq-7000 EPP combines an industry-standard ARM processor-based system with Xilinx 28-nanometer low-power, high-performance programmable logic in a single device. The processing system (PS) provides dual ARM Cortex™-A9 processors, Level 2 cache and on-chip memory, as well as a rich peripheral set sufficient for general-purpose and waveform processing. The programmable logic (PL) provides ample logic cells, configurable memory (dual-port RAM, FIFOs, shift registers, BRAM) and hardware multipliers for DSP which can be utilized for high-speed parallel processing of needed functions.
Yes, there is a way to do red/black separation on one FPGA device. It is called Secure Chip Crypto (SCC), or alternatively the Isolated Design Flow (IDF). Both mean the same thing, and are supported exclusively by Xilinx. Contact an FAE for more details.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.