Three-dimensional integrated circuit (3D-IC) systems offer the potential to deliver significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. Despite substantial progress toward realizing 3D-IC systems, a variety of design, manufacturing, packaging, and testing issues still need to be addressed before cost-effective, high-volume production can be achieved. In this article we will focus on the test challenges and solutions, highlighting a design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute (ITRI) based on the Synopsys test solution.
2.5D before 3D
Advances in manufacturing and packaging technologies have already brought “2.5D” platforms within reach of early adopter design teams: 2.5D IC integration offers the potential to deliver a tighter form factor than standard systems-in-package by mounting multiple dies atop a common electrical interface, called a silicon interposer, and connecting them together with wires that run through the interposer . The system I/Os are connected to the underlying package substrate using vertical Through Silicon Vias (TSVs), essentially cylindrical metal posts that extend partway through the interposer (Figure 1).
But when it comes to delivering on the integration benefits mentioned above, 3D die stacking  holds the greatest promise. With this approach, TSVs are etched deep into the substrate and the wafers thinned down to less than 50 microns. Many dies can then be stacked vertically on top of each other and connected together by TSVs (Figure 2). A combination of the two techniques resulting in a heterogeneous system of multiple die stacks would utilize a silicon interposer to connect all the bottom dies in the same way as 2.5D-IC packages.
Figure 1: 2.5D configuration with silicon interposer
Figure 2: 3D configuration with face-to-back bonding of two stacked dies connected by TSVs
The design of the first 3D-IC systems is now underway, thanks to the development of standards by organizations such as IEEE, JEDEC, SEMI, and Si2 in cooperation with semiconductor and electronic design automation companies. For example, in October 2011 Samsung and Micron Technology announced the creation of a consortium to accelerate industry collaboration for the development of an open interface specification for Samsung’s Hybrid Memory Cube, which delivers “unprecedented system performance and bandwidth” in part by employing vertically stacked memories connected through TSVs. In spite of early progress, a range of technical obstacles still need to be overcome to achieve cost-effective, mass production of 3D-IC systems, and we now turn to the challenges confronted when testing them in a high-volume setting.Testing in 3D
One basic approach to 3D-IC testing involves performing a post-bond test after each die has been bonded to the stack. The goal is to test portions of the system that could have been damaged during the bonding process. Because it is not viable to “un-bond” a die subsequently found to be defective, one study  maintains that performing a separate pre-bond (i.e., standalone) test to identify a Known Good Die (KGD) for stacking is more cost-effective than relying solely on post-bond testing to identify a defective die that has already rendered the entire system defective.
However, the economics of pre-bond testing have yet to be fully characterized, and one of the key challenges is how to apply the KGD test. With the exception of the bottom die, no probe pads exist for pre-bond testing because all the I/Os are accessible only through TSVs topped by fine-pitch micro-bumps, which are arrayed on both sides of the die. Standard probe equipment applies tests on a single side only and even state-of-the-art production systems do not meet the fine-pitch and I/O bandwidth requirements of 3D-ICs. Moreover, it is difficult to perform pre-bond tests without damaging the micro-bumps or deforming the thinned wafers .
Efforts are underway to deliver probe systems that facilitate probing on fine-pitch micro-bumps. Rocking Beam Interposer (RBI) technology  in membrane probe cards improves probing accuracy and minimizes bond pad damage. Contactless probing  may also prove viable. At this time, however, these solutions are still a work-in-progress for meeting 3D-IC probing requirements. Likewise, the test challenges specifically related to handling of thinned wafers and thinned dies remain formidable [4, 7], and in 2010 SEMI created a taskforce specifically to define requirements and develop standards for the reliable handling and shipping of thin wafers.
These and other test infrastructure challenges must be properly addressed before 3D-ICs can be tested cost-effectively in high volume. Yet compared with these challenges, the design-for-test (DFT) challenges for 3D-ICs are much easier to overcome, as we’ll see in the sections that follow.Test Automation Evolves
Although there are new failure mechanisms
due to defects caused by wafer thinning and by TSV filling, alignment, and bonding, their fault effects
appear to be the same as those encountered in two-dimensional (2D) designs. Therefore, conventional stuck-at and transition-delay automatic test pattern generation (ATPG) can be used or extended to test 3D-ICs. For example, slack-based transition delay tests that target small delay defects and bridging tests that target bridging faults are already in use today to meet ultra-high test quality requirements. With the advent of 3D-ICs that offer smaller form factors and higher performance than current 2D designs, these advanced tests—already available in Synopsys’ TetraMAX ATPG product—become necessary for screening 3D systems.
In addition, greater system complexity of 3D-ICs demands tighter control of dynamic power consumption, which differs pre-bond versus post-bond (since TSVs are used to distribute power up the stack in the latter case). Advanced power management techniques such as power-aware ATPG and power domain-based testing are required to control power consumption and avoid false failures during 3D-IC testing. Power-aware ATPG generates patterns that limit both shift mode and capture mode power to functional levels based on a designer-specified power budget. Power domain-based test generates patterns in compliance with a design’s functional power states to reduce both dynamic and leakage power and avoid IR-drop issues. These advanced capabilities in the Synopsys test solution already have been successfully deployed to limit false failures on the tester, and will be essential for managing power during testing of 3D-ICs, which are also susceptible to increased thermal density and thermal variation .
Extensions to existing test automation that address very specific 3D-IC testing requirements include the ability to insert and connect TSV ports and related logic in a design, and the ability to generate “loopback” tests that allow data to be applied to and captured from the TSV I/Os to verify their functionality during KGD testing. For TSV connectivity tests, TetraMAX ATPG uses “dynamic bridging” fault models to generate at-speed patterns that can target time-sensitive shorts between TSV I/Os.