To show how this new approach operates, we will present an example design of a simple two-stage Miller OTA amplifier, as shown in Figure 2, which uses a 65nm technology. To simplify the demonstration, the solution will focus on the WPE effect. However, the same concepts can be easily extended to consider other LDE effects; such as STI effects.
Figure 2: Schematic design of two-stage Miller OTA, biasing network not shown.
Figure 3: The new proposed custom IC Design cycle.
As shown in Figure 3, the design flow, including the interactive LDE estimator module, is as follows:
- Schematic design and functional verification takes place until the design requirements are met.
- Operating point information, from circuit simulation, is collected together with device constraint data (optional) for future use by the LDE estimator module. Device constraints include the allowable variation of threshold voltage “?Vth” and current drive “?I”. Device constraints can be mostly determined based on the designer’s expertise. These constraints can also include matching between selected devices.
- The layout engineer performs layout placement according to the minimum design rules, targeting area optimization.
- The layout executes the LDE estimator module which will do the following steps:
a. Extract the layout dimensions required for the WPE calculations.
b. Pass the WPE dimensions to the LDE checking module that calculates the deviation of the Vth and I of every device. This checking module includes BSIM4 WPE equations that determine the changes in threshold voltage and mobility parameters and a simplified current equation based on a BSIM4 model. This step does not require circuit simulation and uses the OP information collected in an earlier step.
- If ?Vth and ?I are not meeting the pre-defined constraints, then the layout engineer has to move layout devices and check their new ?Vth and ?I using the LDE estimator module until the constraints are met; in this case, the placement step will be concluded, and the layout engineer will start the routing step.
It is important to note that this method does not require circuit simulation during the interactive LDE estimation step and minimizes the design targets dependency on LDEs before proceeding with the routing and physical verification steps.
Now we will validate whether this LDE estimation flow produces good results. To do so, we used the same Miller OTA design and the Pyxis, Eldo, and Calibre IC-design tools from Mentor Graphics.
First, the schematic design has been tuned to obtain the targeted Gain and Bandwidth as depicted in the simulation results shown in Figure 4.
Figure 4: Bode plot for the OTA design.
Second, layout devices are placed according to the minimum design dimensions as shown in Figure 5. On checking the simulation results based on extracted layout, without taking the interconnect parasitics into account, the design targets (Gain and Bandwidth) failed because of the LDE effects, as seen in Figure 4.
Figure 5: Layout on the minimum design dimensions.
Then using the LDE estimator module, as explained before, we were able to reduce the value of the ?Vth and ?I (as seen in Table 1) by moving devices around and figuring out the best layout placement that guarantees smaller deviations from the design targets, as seen in Figure 6.
Figure 6: The layout after using the LDE estimator.
Table 1: ?Vth and ?I values before and after using the LDE estimator module.
Finally, checking the simulation results of the final layout, without routing parasitics, the Gain and Bandwidth are very close to the original pre-layout simulation.
This new approach for estimating LDE effects at an early phase of the design cycle reduces the design cycle significantly. Using the LDE estimator module, users can quickly learn how to achieve better layout placement and boost overall productivity despite LDE snags.
The continual shrinking in layout dimensions has given rise to significant effects that carry interdependencies between neighboring structures. During the past few years, technologists have demonstrated STI related stress to severely disrupt the analog characteristics of MOS devices and, thus, the overall circuit functionality. Careful handling of these effects has therefore become an essential requirement for guaranteeing design robustness. This article discussed a new approach for estimating LDE effects at an early phase of the design cycle. The LDE estimator module introduced was demonstrated to be particularly valuable in bridging the gap between electrical design intent and physical realization. This methodology is expected to boost overall productivity despite the snags imposed by advanced layout dependent effects.
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