Over the past 40 years, the semiconductor industry has continued its rapid pace offering more compact electronic products with higher speed and increasing functionality at lower cost. This rapid growth has been fueled by the industry’s ability to scale MOS transistors as predicted by Moore’s law. Yet, when technology nodes have reached the sub 90nm threshold, performance improvement anticipated from scaling failed to match expectations within the analog design community. This is largely due to the emergence of Well Proximity Effects (WPE) and Shallow Trench Isolation (STI) stress effects that were not accounted for in previous process nodes.
WPE and STI related stresses have been proven to severely disrupt the electrical characteristics of MOS devices. Such effects depend on device placement during the layout design phase, hence the more generic description: layout-dependent effects (LDE). LDEs affect a device’s intended performance and subsequently disrupt system functionality. For this reason, careful handling of these effects at advanced process nodes is necessary to guarantee a design’s robustness.
At nanometer process nodes, analog behavior is highly sensitive to layout interdependencies that rapidly cause intolerable device mismatches—a 10–15% shift in threshold voltage is a common occurrence if LDEs are ignored. However, the associated impacts of these effects on a design’s performance can be seen only after the complete layout is finished; i.e. at the end of the design cycle, which leads to many design iterations. Thus, to reduce these costs and ensure parametric yield at these deep submicron levels, analog designers cannot wait until post-layout verification to analyze layout-dependent effects. Instead, a fusion between electrical and physical effects is needed during the early circuit design cycle.
Unfortunately, today’s class of EDA tools does little to help preserve the designer’s intent against these types of complexities. Designers need layout-aware schematic-level design methods and tools that allow them to access and analyze transistor non-idealities caused by the proximity of neighboring devices and structures in the layout.
A look at the conventional custom IC design flow and its LDE associated challenges gives us some insight to why this new tool and methodology is critical to reducing the design cycle. The conventional design flow can be divided into two phases: a front end, which starts with circuit schematic design followed by performance verification through simulation, and a back end phase, during which the layout is created through placement and routing, followed by a physical verification step that results in the extraction of a parasitics-annotated netlist. This back-annotated netlist is re-simulated to check for possible deterioration of design targets.
Figure 1: Conventional custom IC design cycle.
More often than not, deviations from the original design targets take place, which calls for several iteration cycles between the front-end and back-end phases until the design finally converges on the spec. Such deviations are mainly due to both LDE effects and routing parasitics. In above 90nm technology nodes, the LDE effects were considered second order effects. The main layout challenge was focused only on reducing routing parasitics. However, below 65nm, layout-dependent effects have a significant impact on a device’s threshold voltage and carrier mobility, which degrades device matching and, hence, overall design performance. Solving these LDEs usually requires replacement, or at least shifting locations of some devices, which then requires re-routing and, hence, increases the complexity of each design cycle.
A promising and innovative solution is interactive LDE estimation. During custom layout creation, interactive LDE estimation finds the deviation from nominal values of the threshold voltage and the drain current for each transistor. When the allowable ranges for such parameters are already known, possessing this information gives layout engineers the knowledge to achieve optimum device placement with respect to circuit performance. Without resorting to any performance simulation, the layout engineer is now able to see the magnitude of such deviations when any of the devices are moved. Hence, device placement with minimum impact on design performance can be easily determined in an efficient way.
During custom layout design, an interactive layout-dependent effect estimation tool is able to quantitatively estimate actual threshold voltage and current deviations from intended values resulting from a given device placement in an interactive manner. This can be more valuable if the circuit designer provides permissible ranges and constraints on transistor threshold voltage and current for critical devices. This solution provides layout design engineers with an interactive estimator for the LDE impact on electrical device behavior while taking device placement decisions. Accordingly, LDE impact on overall design performance can be minimized before starting the routing step.