The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due to ASIC design complexity. To overcome the risk of re-spins, high NRE costs, and to reduce time-to-market delays, it has become very important to design the first time working silicon.
This chapter constitutes a general set of recommendations intended for use by designers while designing a block or an IP (Intellectual Property). The guidelines are independent of any CAD tool or silicon process and are applicable to any ASIC designs and can help designers to plan and to execute a successful System on Chip (SoC) with a well-structured and synthesizable RTL code.
The current paradigm shift towards system level integration (SLI), incorporating multiple complex functional blocks and a variety of memories on a single circuit, gives rise to a new set of design requirements at integration level. The recommendations are principally aimed at the design of the blocks and memory interfaces which are to be integrated into the system-on-chip.
However, the guidelines given here are fully consistent with the requirements of system level integration and will significantly ease the integration effort, and ensure that the individual blocks are easily reusable in other systems. These guidelines can form as a basis of checklist that can be used as a signoff for each design prior to submission for fabrication.
The book preface can be found here.
If you are interested in purchasing the book, it is available from Amazon
We started with Chapter 2 Part 1 which included:
2.2 Synchronous Designs
2.2.1 Avoid Using Ripple Counters
2.2.2 Gated Clocks
2.2.3 Double-Edged or Mixed Edge Clocking
2.2.4 Flip Flops Driving Asynchronous Reset of Another Flop
Then we covered Chapter 2 part 2 which included:
2.4 Clocking Schemes
2.4.1 Internally Generated Clocks
2.4.2 Divided Clocks
2.4.3 Ripple Counters
2.4.4 Multiplexed Clocks
2.4.5 Synchronous Clock Enables and Gated Clocks
2.5 Clock Gating Methodology
2.5.1 Latch Free Clock Gating Circuit
2.5.2 Latch Based Clock Gating Circuit
2.5.3 Gating Signals
2.5.4 Data Path Re-ordering to Reduce Switching Propagation
Last week we examined Chapter 2 Part 3 which included:
2.6 Reset Design Strategy
2.6.1 Design with Synchronous Reset
2.6.2 Design with Asynchronous Reset
2.6.3 Flip Flops with Asynchronous Reset and Asynchronous Set
2.6.4 Asynchronous Reset Removal Problem
2.6.5 Reset Synchronizer
2.6.6 Reset Glitch Filtering
We conclude with Chapter 2 Part 4 that looks at clock skew:
2.7 Controlling Clock Skew
2.7.1 Short Path Problem
2.7.2 Clock Skew and Short Path Analysis
2.7.3 Minimizing Clock Skew
is a Senior Systems Engineer with Freescale Semiconductor. Since
joining Freescale in 2005, he has been responsible for IP/SoC
Architecture and has led the design and development of various SoCs for
multimarket segment. As a systems engineer, he has been involved in
product definition and writing specifications, MCU/MPU-based products
for the mid-high end industrial and consumer market space. Prior to
joining Freescale, he worked for Agilent Technologies, ST
Microelectronics and DCM Technologies as a design engineer and lead,
focused on printing ASICs, USB2.0 PHY, PCI-Express, Infiniband and
Serial ATA protocols. You can visit his website here.
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