Last month, JEDEC hosted a mobile memory event at 2012 Consumer Electronics Show. One of the presenters was Cecil Ho President of CST and a member of the JEDEC Board of Directors. I recently spoke with Cecil about the challenges of testing mobile memories, and he gave me his perspective from his vantage point at CST.
Test&Measurement Designline (T&M DL): What's the typical form factor for mobile memories? Why is this packaging choice so attractive? Cecil Ho: To save precious space, mobile memories come in a BGA (ball grid array) package. They are usually constructed with multiple dies stacked on each other. It is generally called MCP (multi-chip package). The chips are interconnected through bond wires.
T&M DL: Are there standard multi-chip packages for mobile memory? How do they differ? Ho: JEDEC has published several package standards for mobile memory. The packages and pinout are keyed on DRAM technology with some optional pins for adding flash combinations. However, due to the many possible variation of flash technology, different vendors' MCPs can be quite different from each other.
T&M DL: Why are MCPs difficult to test? MCPs combine different kinds of memory technologies, namely DRAM and flash. The conventional test method for the two separate memory technologies are quite different. The convention method is to use a "two pass" tester and two teams of test engineers for their separate expertise.
T&M DL: What kinds of tests need to be done? Why? Indeed, MCPs test need not be complicated. Since the DRAM and flash chips are already tested by their original vendor, only a functional test is required to detect assembly error and die handling damages.
T&M DL: How are MCP for mobile applications typically tested? Today, most MCP chips for mobile applications are tested with general purpose memory ATE (Automated Test Equipment). It is usually done with a "two pass" test.
T&M DL: What are the limitations of this approach? The memory ATE testers are bulky, expensive, and less flexible. They usually require high levels of engineering skill in maintenance and reconfigurations. Besides, as mobile memories are getting in production high-gear, there will be a shortage of testers to fill the production test needs.
T&M DL: Is there an alternative way to test? How is that an advantage? Who is doing it? The alternative is to use a functional tester built for MCP testing. Our company is making such a tester. The advantage is low cost, small footprint, and easy configuration. It can also run simultaneous (single pass) tests on both DRAM and flash to weed out cross-talk problems on the assembly.
T&M DL: Can you talk us through an example of an alternative test set up? A typical CST MCP Test System has 64 DUT (device under test) sockets. It is integrated with a pick-n-place chip handler for automation. Once all the chips are loaded into the sockets, the tester will exercise the cell contents of the chip including the DRAM and the flash contents. It then reports the errors through its host PC display. It pin-points the fault as well as saving a log for failure analysis.
T&M DL: What needs to be done for DRAM testing? Typical mobile DRAM are LPDDR1 (low power), LPDDR2, and the upcoming LPDDR3. DRAM testing involves a read/write on each cell at high speed up to 1600 MHz (LPDDR3). Due to possible DRAM soft errors, different critical test patterns also have to be run to unveil those failures.Our tester uses FPGA based pattern generators to generate flexible vectors to fill the needs.
T&M DL: What about non-volatile testing? Non-volatile flash testing is normally read/write/erase, and bad cell marking. However, due to the new generation of Toggle Mode and ONFI NAND flash, double-data-rate high speed accessing also has to be included.
T&M DL: Concerns when testing eMMC? eMMC testing is different from raw NAND. In the previous case, it involves a controller between the host and the NAND flash chips. In additional to read/write/erase, there is also formatting and cell counting. On top of that, eMMC involves security features that require information to be pre-written into internal registers. The tester must be able to fulfill this function also.
T&M DL: How is UFS testing different? UFS is similar to eMMC with the exception of the serial interface bus. The tester will have to include a high speed Serte to convert this high speed serial data to the tester common interface and vise versa.
T&M DL: What challenges remain for mobile memory testing? Mobile memory is a rapidly changing industry. New memories are expected to appear every 18 months. Each generation will come with higher speed and lower power. The challenge is to keep up with the repaid changes and have test solutions ready to meet the challenge.
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