The increasing opportunities and requirements for system-in-package (SiP) technologies have become a driving force in the electronics and semiconductor industry. A number of companies are focused on maximizing the benefits and meeting the challenges that SiP brings.
Some SiP technologies, such as wirebonded multichip modules and advanced MCMs, have been around for decades; others, such as package-on-package stacking, are more recent. Such newer technologies as 2.5-D interposers and 3-D through-silicon via (TSV) can bring new challenges along with new capabilities.
Depending on the design and application space, SiPs can:
• improve performance with tighter integration and co-design;
• increase power efficiency, with shorter data transmission channels;
• enable heterogeneous integration via different technologies;
• lower total cost by reducing the system size and bill of materials (BOM);
• reduce complex system-on-chip (SoC) development for shorter time-to-market; and
• miniaturize devices by stacking components, vs. side-by-side layout.
But SiP products also have unique challenges.
As data density, bandwidth and frequency increase, electrical parasitics must be reduced. This generally requires shorter data paths and more of them, which means finer pitches. These form factors, pitches and mechanical structures drive the interconnection technologies required by the SiP solution.
Such adjustments to design and fabrication must take into account equipment capability and cost, bonding accuracy and yield, as well as advanced materials.
Reaching the required quality, cost and yield calls for a new approach to process, equipment and materials. One challenge of SiP implementation is that the devices to be integrated often arrive in different formats, such as wafers, individual units or intermediate carriers.
To reach higher performance levels and density, devices often need to be designed, simulated and fabricated in parallel with the SiP solutions. For high-frequency data paths, that means leveraging shorter chip-to-chip distances with low-latency interconnections to improve power efficiency and reduce die area.
I/O definition (planning, placement and optimization) and 3-D floor planning become more critical in the early phases of the design flow. Increasingly, co-design is required across divergent tool platforms, teams or design functions, and even across different companies. This adds time and uncertainty to the design process.
It is important to test the intermediate and final process steps to get the best yield, quality and cost. Intermediate testing can be difficult because the process steps have
various formats, and pieces have to be tested apart from the whole. Final testing can be difficult because a more-complex final device requires more-complex and more-costly equipment and algorithms to evaluate proper functionality.
One solution is proactive design-for-test (DFT) on each part of the product.
The need for standardization of advanced SiP technologies will grow as design, packaging, device processing and test become more fragmented and cross boundaries among companies and working environments. Standardization across the process toward final product is often uncharted territory.
All these challenges affect costs for engineering, equipment, manufacturing, procurement and liability for quality and yield. The semiconductor market encourages companies to focus on what they want and outsource the rest. In an SiP environment with more devices and complex intermediate processes, many production models must be redefined. That affects the financial decisions involved in product development, especially for companies with less ability or penchant for investment in unproven solutions.
Five levels of complexity
There are five levels of complexity in SiP solutions, depending on the implementation considered and the benefits to be achieved.
Wirebonded MCMs (Figure 1) bring greater levels of miniaturization, integration and performance at lower cost. They combine many types of devices—such as digital and analog ICs, sensors, passives, microelectromechanical systems (MEMS) and power-management components—in a single package. Two-dimensional implementations place all the devices next to each other; 3-D implementations stack some devices vertically. Among the improvements to this well-established technology are leadless, wafer-scale, ultrathin form factors; copper wires; and improved processing and design capabilities.
Figure 1. Multichip modules with wirebond packages. Click on image to enlarge.
Advanced MCMs (Figure 2) are relatively quick and practical to implement. They offer many innovative possibilities, such as use of embedding to combine ICs and passives in a very small footprint or a dramatic reduction in the resistance and inductance of power MOSFETs by stacking them with thick copper clips. Because they incorporate advanced interconnection methods such as solder printing or plating, lamination or metal depositions, they require more manufacturing steps, along with careful co-design for manufacturing and reliability.
Figure 2. Multichip modules with advanced interconnect methods. Click on image to enlarge.
Package-on-package technology (Figure 3) allows each package to be built and procured separately. Each chip can be packaged in optimal fashion (often including MCM options already mentioned) and combined in advance or in the end system. This requires concurrent dual-level surface-mount technology (SMT) in the end system with careful control of warpage over temperature. It also requires standardization for co-design across supply chains. Many applications use package-on-package technology, which continues to advance in thickness and warpage control while integrating more functionality in each package.
Figure 3. A package-on-package device. Click on image to enlarge.
The 2.5-D interposer SiP brings ICs even closer together physically and electrically through finer design features and technologies. Passive interposers use wafers, such as silicon or glass patterned with lithography and with vias through them, along with flip-chip interconnection to a substrate. There are great challenges and many industry initiatives involved in moving to this level of SiP integration. Additional wafer processes, such as wafer carriers and die-to-wafer bonding, must be integrated with the traditional wafer and packaging processes.
The 3-D TSV (Figure 4) allows direct physical stacking with high-density connections. In 3-D technology, TSVs are applied to active IC wafers and stacked directly.
Figure 4. 2.5-D interposer and 3-D TSV examples. Click on image to enlarge.
Though many core technologies are already implemented in some markets, broader implementation requires the challenges of 2.5-D technology to be fully resolved through co-development and co-design. This holds especially true in instances where the IC or ICs with TSVs are also complex and costly, as is the case with processors or high-density memory.
Choosing an SiP solution is a function of applications space, system requirements, yield and cost. New SiP solutions continue to emerge every day. SiP may truly be the technology that most determines the pace and the form of many electronics trends for the next decade and beyond.
About the authors
Matt Romig (firstname.lastname@example.org) is packaging technology productization manager for TI Analog. He holds a BSME degree from Iowa State University, Ames.
Vikas Gupta is a packaging engineer in the Application Specific Products Group at TI. He holds a PhD from the University of Missouri, Rolla.