The standard for Wide I/O mobile DRAM, released by Jedec in January, uses through-silicon vias (TSVs) to connect DRAM to logic on three-dimensional integrated circuits. With its 512-bit data interface, JESD229 Wide I/O Single Data Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.
Devices that use TSV connections between homogeneous dice are already available. Wide I/O is leading the way to TSV connections between heterogeneous dice.
Among the companies offering devices with homogeneous TSV connections are Xilinx, whose Virtex-7 2000T field-programmable gate arrays use logic connected to logic, and Samsung, whose 32-Gbyte registered dual-in-line memory modules (RDIMMs) use DRAM stacked with DRAM. There are many good reasons for homogeneous TSV connections. Xilinx claims its devices offer a hundredfold improvement in die-to-die connectivity bandwidth per watt with one-fifth the latency; Samsung claims a 40 percent reduction in power.
Even a device that has twice as many cells on it than the dice we can produce today can use TSVs to connect two homogeneous dice. But what happens when a device has more types of different cells than the dice we can produce today?
The full potential of TSV technology comes with the ability to connect dice with different physical properties. Though it is possible to put logic, memory, radio-frequency (RF), analog, power, and image-sensing circuits all on the same piece of silicon, it may be preferable to put them on separate dice for the best performance at the lowest cost.
Figure 1. A 3D-IC using TSVs.
Click on image to enlarge.
Like many new technologies, TSV has an initial cost that is higher than the technology it replaces, and simply reducing the cost of the dice in the stack may not be enough to justify its use. The ideal applications for TSV technology are those that can benefit from the dramatic improvement it brings to bandwidth, latency and power.
Consider the interface between the logic die and DRAM in a next-generation smartphone, tablet or subnotebook. These next-generation devices will require about 100 Gbits/second of peak bandwidth between logic and DRAM, which is the highest-bandwidth chip-to-chip interface typically found inside this class of product. Many logic manufacturing processes include the ability to create some embedded DRAM. But it is substantially cheaper to produce large amounts of DRAM on a dedicated DRAM process.
Today’s 2-Gbit DDR3 devices, each of which contain 2 billion transistors, can sell for less than a dollar per chip, easily meeting the economic test for making the logic die and the DRAM die on different processes. Because memory latency is a key metric in the performance of systems-on-chip (SoCs), a low-latency DRAM interface is desirable. In a smartphone, the DRAM under heavy load can consume 25 percent of all power used: any reduction in power per bit transferred can substantially improve battery life.
The Wide I/O standard takes full advantage of 3-D die stacking by significantly improving performance and power. By using low-speed low-capacitance connections, Wide I/O transmits data at about half the power per bit of LPDDR2. By using a broad array of I/Os, Wide I/O doubles the bandwidth of a two-channel LPDDR2 connection to reach 100 Gbits/second.
Figure 2. Low-power DRAM bandwidth per package, by year of introduction.
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For an idea of how LPDDR2 could be used to achieve 100 Gbits/second of memory bandwidth, consider a representative smartphone with half of its mass and volume dedicated to the battery. Assume that the DRAM uses 25 percent of active power. Keeping everything else equal and battery life the same, doubling the DRAM bandwidth to 100 Gbits/second with LPDDR2 would increase battery size by 25 percent. The resulting phone would be heavier and 12.5 percent thicker than the previous generation. Wide I/O would double the bandwidth at the same power as LPDDR2 with no impact on the mass or volume of the phone.
In December 2011, ST-Ericsson, CEA-Leti, STMicroelectronics and Cadence Design Systems announced their collaboration in the Wide IO Memory Interface Next Generation (Wioming) project, an effort to produce a three-die stack using Wide I/O connections between logic and DRAM. The Cadence role was to provide the electronic design automation tools for the chip design and stack construction as well as to develop the project’s memory controller.
Figure 3. Diagram of the Wioming 3-D IC stack.
Click on image to enlarge.
Along with the manufacturing and packaging capability required to produce TSVs, the Wide I/O ecosystem requires high-quality design image processors (IPs) for the memory controller and physical layer (PHY). Since the DRAM is a major contributor to performance and a major consumer of system power, Cadence is using its expertise in low-power DRAM controllers to develop the Wide I/O controller.
Test is another key area of the Wide I/O ecosystem. In June, Cadence and IMEC announced an automated test methodology for the connections in 3-D stacks. Though JESD229 specifies boundary scan for Wide I/O DRAM, it does not mention how to test the memory array itself. In a typical TSV stack construction flow, the DRAM must withstand harsh treatment during wafer thinning, TSV formation and stacking. Even with known-good dice from the memory vendor, it becomes essential to test the DRAM array after stacking.
The Cadence approach extends the memory built-in self-test (BIST) engine already integrated with the memory controller, enabling the detection of new classes of DRAM errors that result from the TSV process.
About the authors
Marc Greenberg is director of product marketing for the SoC Realization Group at Cadence. Greenberg represents Cadence at Jedec. He holds a master’s degree in electronics from the University of Edinburgh in Scotland.
Samta Bansal is senior manager of product marketing for the SoC Realization Group at Cadence, where she leads the company’s 3-D IC efforts. Bansal holds a bachelor’s degree in electrical engineering and a master’s degree in physics from Birla Institute of Technology and Science, Pilani (India). She also holds a master’s degree in business from Santa Clara (Calif.) University.