RF board design is as much about keeping signals out of the places they don't belong as it is about getting signals to the places they do belong. It requires conscious effort to keep signals isolated to their intended portion of the signal path. Tones, signals, clocks, and all of their harmonic products generated anywhere on the board have a tendency to sneak into output signals as spurs, or worse, into mixers and converters where they get shifted, reflected, and aliased into spurs. Transmit mask requirements mean that even the tiniest spurs can block release of a product.
The importance of spur reduction is compounded by today’s trend towards software-defined radio (SDR) enabled by wideband devices. Because a single platform design can be deployed to address multiple frequency bands, plug-in RF modules are being displaced by larger boards where more signals can interfere with each other. Small plug-in RF modules, including most RF vendor evaluation modules, are completely isolated and exhibit extraordinary spur performance, but use special design techniques. Myriad vias, topside routing, dedicated ground planes, and other layout techniques that work brilliantly for small RF boards often do not scale well.
Low spur RF layout often depends on the intuition of an RF engineer, because layout tools are optimized for large scale layout, not electromagnetic analysis. Usually basic rules are applied during layout and board review, but the real test only comes around once a board has been prototyped and is under evaluation in the lab. After basic board functions, such as power level and linearity, have been checked, evaluation of spurious performance becomes the focus. At this late stage, spurs require the RF engineer, who works the "black magic" to identify a root cause and a fix. Not only is such debug time nearly impossible to predict and schedule, but the fix often involves a board spin, which incurs project delay and expense.
Most of the RF engineer's intuitive rules are based on simple principles that can be applied during the layout review. Keep these eight rules in mind to get product shipped faster with more predictable schedules.
Rule 1: Place ground vias at ground reference plane switches
Every current that flows along a routed line has an equal return current. While there are many strategies for coupling, the return current generally flows through an adjacent ground plane or in a ground that is routed alongside the signal line. When this reference plane is continuous, all coupling is restricted to the transmission line and everything works great. But when the signal line switches from topside to an inner or bottom layer, the return current must also be given a path.
The situation is illustrated in Figure 1. Current in a signal line on the top layer sees a companion return current immediately below. When it transitions to the bottom layer, the return current goes through a nearby via. However, when there is no nearby via for the return current, it travels to the closest available ground via. The extra distance creates a current loop that acts as an inductor. The interference is made even worse if the undesired current path excursion happens to cross over another line. Another word for a current loop like this: antenna!
Figure 1: Signal current flows from the device pin, through a via, to a lower layer. The return current travels under the signal until it is forced to flow to the nearest via to change onto a different reference plane.
Ground reference is the best policy, but, on occasion, a high-speed line may be routed on an internal layer. It is very difficult to place ground reference planes both above and below or pin constraints may force a semiconductor manufacturer to set a supply line next to a high speed line. Any time that a reference current needs to switch between layers or nets that are not DC-coupled, place the decoupling capacitance immediately adjacent to the switch point.Rule 2: Connect device pads to topside grounds
Many devices include thermal ground pads on the bottom of the device package. On RF devices, these are generally electrical ground and the adjacent pad is dotted with an array of ground vias. Connect the device pad directly to ground pins and to any copper pour through topside ground. When presented with multiple paths, return current splits in proportion to the impedance of the paths. The ground connections through the pad may provide a shorter path or lower impedance than pin grounds.
Good electrical connection between the board and device pad is critical. During assembly, unfilled vias in the array of board vias can also wick solder paste away from the device, leaving voids. Filled vias are one excellent strategy for keeping solder in place. During review, also turn on the solder mask layer to verify that no solder mask is placed on the board ground under the device, because solder mask tends to elevate or float the device.