In medical applications such as magnetic resonance imaging (MRI), ultrasound, CT scanners, and digital X-ray, high channel-count analog-to-digital converters (ADCs) are used to sample large arrays of data. Serial interfaces are used to acquire the sampled data to reduce the number of pins on the ADC and FPGA.
In addition, routing of a high speed serial interface saves board space. With board real estate at a premium and FPGA pins a valuable commodity, the advantages of serial data converter interfaces over parallel are clear.
Today, there are two choices of serial interfaces that are suitable for high-speed data converters. The first is a serial clock-data-frame (CDF) interface, which combines a serialized LVDS (low voltage differential signaling) data stream, as well as a differential clock to accurately collect this data and a framing clock to establish data sample boundaries. The second choice uses the JESD204 standard, where the clock is embedded into a high-speed gigabit-per-second (Gbps), two-wire serial data stream.
Each interface has its advantages and disadvantages. Because of the higher power requirement of the current mode logic (CML) pairs used to drive the high speed JESD204 interface, serial LVDS is preferred for lower-power, high channel count and portable designs. But it takes over where serial LVDS leaves off. The choice between serial LVDS and JESD204 interface standards will depend on power consumption requirements and availability of SerDes ports on the FPGA.
"Serial interfaces for high-speed A/D Converters," which was previously published at EE Times-Europe, looks at the benefits of serial LVDS, the JESD204 high-speed serial interface standard, and advantages compared to typical 6-wire serial transmission.
About the author
Alison Steer is Product Marketing Manager at Linear Technology Corp.(Milpitas, CA).