A growing set of IC applications require a high voltage interface. Examples include power management, power conversion and automotive chips with interfaces typically between 12 V and 100 V. Also, mobile devices like cell phones and personal navigation devices today include interfaces above 10 V to, e.g., control and sense MEMS gyroscopic or compass sensors. And most LCD/OLED display technologies require driving voltages between 10 and 40 V. Besides the power, MEMS, and display interfaces, many devices include some sort of motor like the optical zoom lens and shutter control of digital cameras or the ‘silent mode’ vibrator in cell phones.
Though these applications represent fast-growth markets, the underlying silicon process technologies lack standardized high-performance ESD solutions. The purpose of ESD protection is to provide a safe, robust current path while limiting the voltage drop below the critical voltage determined by the circuit to be protected. Today, different protection clamp types are used in the industry, each with significant performance and cost burdens that prevent generic use. The main problems with traditional solutions are high leakage current, large silicon area consumption, and extensive custom (trial and error) development cycles for each process/fab change.
Despite the efforts from the ‘ESD council’ to reduce the component-level ESD performance levels [1-2], there is an opposing trend to push system-related ESD/latch-up requirements down to the IC design level in order to reduce system failures and improve user safety [3-4]. This is most prevalent in automotive, industrial and consumer electronics markets. OEMs request very robust and latch-up immune on-chip ESD protection devices .
Requirements for high voltage ESD clamps
Foremost, an ESD clamp needs to protect the chip circuitry. The circuit can be an entire power domain (supply pin protection) or a single input, output, or I/O circuit (I/O pin protection).
ESD protection is typically qualified using human-body model (HBM), machine model (MM), and charged-device model (CDM) testers. For an in-depth analysis however, Transmission Line Pulse (TLP) testers are used to characterize the ESD relevant performance parameters of the protection clamps as shown in Figure 1.
Figure 1: Generic clamp behavior based on TLP analysis. The clamp remains off until the trigger voltage ‘Vt1’ is reached. The clamping mode is characterized by a holding voltage ‘Vh’ and the on-resistance ‘Ron’. The clamp failure current is called ‘It2’.
While ESD devices are routinely characterized with TLP to determine their optimal design, additional analysis is required. There are 4 main problems with TLP measurements that are relevant for this discussion:
- The TLP characteristic is based on averaged values of voltage and current waveforms versus time; hence the TLP IV curve hides relevant time dependent behavior [6-8].
- The TLP pulse width is typically limited to 100 ns; that is enough for ESD-relevant analysis, but it is not relevant for electrical overstress (EOS), which has a much larger timeframe.
- TLP measurements are performed on 2 pins, leaving other pins floating. No bias is applied at VDD and many latch-up issues remain undetected .
- Most commercial TLP systems have 50-O characteristic impedance, not suited for analysis of high-voltage snapback clamps [8, 10].
Therefore, in addition to standard TLP analysis, it is important for high-voltage applications to look carefully into the full waveform information and to include longer pulse durations in the evaluation. This is evident from Figure 2: the voltage versus time waveform of the High Voltage SCR (large anode-cathode spacing) shows that the device has a clamping regime well above VDD for the first 100 ns (TLP time domain – highlighted by the rectangle). However the clamp voltage decreases below the VDD voltage for longer pulse duration. This means that latch-up issues may occur when this device is used as ESD protection clamp under transient latch-up situations like some EOS and IEC 61000-4-2 stress situations.
Figure 2: Voltage versus time waveform characterization of a basic high-voltage SCR device in 0.35-µm 15-V CMOS. The voltage waveform is measured with a TLP-like setup using solid-state pulse generators with a much longer pulse width (500 ns instead of the TLP standard 100 ns duration). Within the 100-ns TLP window, the measured holding voltage is high enough, however the voltage drops below the supply level after 250 ns… which can lead to latch-up.
Other measurement approaches exist to verify the transient latch-up susceptibility. Professor Ker from Taiwan, for instance, tends to use a system depicted in Figure 3 [11-13]. First, a DC bias of VDD (40 V in the example) is applied to the device under test. Secondly, a sharp pulse is superimposed on the DC level by connecting a charged capacitor to the biased device. Such a test has many different names depending on actual conditions: Vlatch, Charged Capacitance Latch-up (CCL) , transient latch-up , or ESD/Machine Model (MM) under powered conditions. It can also be simulated with a multi-level TLP approach . Due to this pulse, the ESD protection clamp will turn on to shunt the ESD current. If the clamp is latch-up immune, the voltage returns to the initial DC bias level once the superimposed MM pulse is over. When performing such transient latch-up tests, it is important to use a fast and low-resistance power supply for the DC bias.
When such a test is applied on a HV grounded-gate (gg) NMOS device, the latch-up problem is clearly demonstrated (Figure 3 bottom). After the ESD pulse, the voltage quickly drops to a low value of about 7 V and remains latched at that low value until the end of the test or failure of the NMOS device.
Figure 3: Transient latch-up setup described by professor Ker (top). A charged 200-pF capacitor is discharged into a biased device under test. When such a pulse is imposed on a HV-NMOS device in a 40-V technology, the latch-up problem is clearly visible (bottom).
Finally, in real world applications, end-user systems can receive multiple ESD stress pulses over the product lifetime. HV-NMOS-based protection devices are prone to degradation issues. The example given below (Figure 4) shows two TLP measurements of identical grounded-gate HV NMOS snapback clamps in a 0.5-um (43-V) technology .
After snapback, at roughly 73 V, a clear and steady degradation is visible in the leakage current. Different TLP stress step levels are used. The data shows that the final failure current (device leakage in µA order of magnitude) is dependent on the pulse density . When a small stress step is applied, the failure current is much lower.
Figure 4: TLP curves on HV-NMOS devices in a 0.5-um 43-V process technology. The TLP stress is applied to 2 identical devices, one with large steps (low pulse density) and one with small steps (high pulse density). Due to the degradation effect, the number of stress pulses strongly influences the failure current It2.